MAXQ612_1 Datasheet, PDF (9/31 Pages) Maxim Integrated Products – 16-Bit Microcontrollers with Infrared Module and Optional USB

16-Bit Microcontrollers with
Infrared Module and Optional USB
I²C BUS CONTROLLER TIMING
(Notes 6, 21) (Figure 2)
PARAMETER
I²C Bus Operating Frequency
System Frequency
I²C Bit Rate
Hold Time After (Repeated) START
Clock Low Period
Clock High Period
Setup Time for Repeated START
Hold Time for Data (Notes 22, 23)
Setup Time for Data (Note 24)
SDA/SCL Fall Time (Note 20)
SDA/SCL Rise Time (Note 20)
Setup Time for STOP
Bus Free Time Between STOP and
START
Capacitive Load for Each Bus Line
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
SYMBOL
fI2C
fSYS
fI2C
tHD:STA
tLOW_I2C
tHIGH_I2C
tSU:STA
tHD:DAT
tSU:DAT
tF_I2C
tR_I2C
tSU:STO
tBUF
CB
VnL_I2C
STANDARD MODE
MIN
MAX
0
100
0.90
fSYS/8
4.0
4.7
4.0
4.7
0
3.45
250
300
1000
4.0
4.7
400
0.1 x VDD
VnH_I2C
0.2 x VDD
FAST MODE
MIN
MAX
0
400
3.60
fSYS/8
0.6
1.3
0.6
0.6
0
0.9
100
20 + 0.1CB
300
20 + 0.1CB
300
0.6
1.3
400
0.1 x VDD
UNITS
kHz
MHz
Hz
Fs
Fs
Fs
Fs
Fs
ns
ns
ns
Fs
Fs
pF
V
0.2 x VDD
V
Note 1: Specifications to 0NC are guaranteed by design and are not production tested.
Note 2: VPFW can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V Q3%. The values
listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal.
Note 3: It is not recommended to write to flash when the supply voltage drops below the power-fail warning levels, as there is
uncertainty in the duration of continuous power supply. The user application should check the status of the power-fail
warning flag before writing to flash to ensure complete write operations.
Note 4: The power-fail warning monitor and the power-fail reset monitor are designed to track each other with a minimum delta
between the two of 0.11V.
Note 5: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals
is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is
achieved.
Note 6: Guaranteed by design and not production tested.
Note 7: IS1 is measured with the USB data RAM powered down.
Note 8: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles.
Note 9: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or VDD. Outputs do not source/
sink any current. The device is executing code from flash memory.
Note 10: Current consumption during POR when powering up while VDD is less than the POR release voltage.
Note 11: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected.
Note 12: The maximum total current, IOH(MAX) and IOL(MAX), for all listed outputs combined should not exceed 25mA to satisfy the
maximum specified voltage drop. This does not include the IRTX output.
Note 13: External clock frequency must be 12MHz to support USB functionality. Full-speed USB(12Mbps)-required bit-rate accu-
racy is Q2500ppm or Q0.25%. This is inclusive of all potential error sources: frequency tolerance, temperature, aging,
crystal capacitive loading, board layout, etc.
Note 14: Programming time does not include overhead associated with utility ROM interface.
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