MAX9526_10 Datasheet, PDF (9/38 Pages) Maxim Integrated Products – Low-Power, High-Performance NTSC/PAL Video Decoder

Low-Power, High-Performance
NTSC/PAL Video Decoder
Pin Description
PIN
QSOP
TQFN-EP
1
30
2
31
3
32
4
1
5
2
6
3
7
4
8
5
9
6
10, 22
11, 23
12
7, 21
8, 22
10
13
11
14
12
NAME
FUNCTION
V_IN1
Single-Ended Composite Video Input 1. AC-couple the input video signal with a 0.1µF
capacitor.
V_REF
Video Reference Bypass. Bypass V_REF to AGND with a 0.1µF capacitor as close as
possible to the device.
V_IN2
AGND
Single-Ended Composite Video Input 2. AC-couple the input video signal with a 0.1µF
capacitor.
Analog Ground
AVDD
Analog Power-Supply Input. Connect to a +1.8V supply. Bypass AVDD to AGND with a
0.1µF capacitor.
XTAL2 ^{External Crystal. Connect XTAL2 to one terminal of the crystal oscillator. Ground XTAL2}
when applying an external clock to XTAL/OSC.
XTAL/OSC
External Crystal/Oscillator. Connect XTAL/OSC to one terminal of a crystal or an
external clock source. Connect XTAL2 to the other terminal of the crystal oscillator.
I.C. Internal connection. Connect to DGND.
DEVADR
I²C Device Address Select Input. Connect to DVDD, DGND, or SDA to select 1 of 3
available I²C slave addresses (see Table 5).
DVDD
DGND
SDA
Digital Power-Supply Input. Connect to a +1.8V supply. Bypass DVDD to DGND with a
0.1µF capacitor in parallel with a 10µF capacitor.
Digital Ground. Connect both DGND terminals together.
I²C-Compatible Serial-Data Input/Output. Connect a 10kΩ pullup resistor from SDA to
DVDDIO for full output swing.
SCL
I²C-Compatible Serial-Clock Input. Connect a 10kΩ pullup resistor from SCL to
DVDDIO for full output swing.
Hardware Interrupt Open-Drain Output. If not masked, IRQ is pulled low when the bits
IRQ
in the status register change state. Repeated faults have no effect on IRQ until IRQ is
cleared by reading the corresponding status register. Connect a 10kΩ pullup resistor
from IRQ to DVDDIO for full output swing.
15–20, 25–28
13–16, 18,
19, 24, 26,
27, 28
D0–D9
Digital Video Outputs Bit 0–Bit 9, 10-Bit Component Digital Video Outputs. The output
format is 10-bit ITU-R BT.656, 4:2:2 with embedded sync. D1 and D0 can be
configured as horizontal and vertical sync outputs using the Clock and Output register
0x0D. D0 is LSB.
Line-Locked 27MHz Clock Output. With line-locked mode, the LLC clock varies in
21
20
LLC response to horizontal line rate of the incoming video. In async mode, the LLC clock is
synchronous to the crystal (see Table 1).
24
23
DVDDIO
Digital I/O Power-Supply Input. Accepts a +1.7V to +3.45V voltage input. Bypass to
DGND with a 0.1µF capacitor.
—
9, 17, 25, 29 N.C. No Connection. Not internally connected.
—
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to GND.
_______________________________________________________________________________________ 9