MAX5936 Datasheet, PDF (9/23 Pages) Maxim Integrated Products – -48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE

-48V Hot-Swap Controllers with V_IN
Step Immunity and No R_SENSE
C_IN = 100µF
V_IN
20V/div
V_GATE
1V/div
4ms/div
Figure 2. GATE Voltage Clamp During Power-Up
ALL VOLTAGES
REFERENCED TO GND ^VEE
20V/div
V_LP
20V/div
V_OUT
20V/div
40ms/div
Figure 3. Load Probe Test During Initial Power-Up
In a normal power-up GATE cycle, the voltage at V_OUT
(referenced to V_EE) ramps to below 74% of the circuit-
breaker threshold voltage, V_CB. At this time, the remaining
GATE voltage is rapidly pulled up to full enhancement.
PGOOD is asserted 1.26ms after GATE is fully enhanced
(see Figure 4). If the voltage at V_OUT remains above 74%
of the V_CB (when GATE reaches 90% of full enhance-
ment), then a power-up to fault management fault has
occurred (see Figure 5). GATE is rapidly pulled to V_EE,
turning off the power MOSFET and disconnecting the
load. PGOOD remains deasserted and the MAX5936/
MAX5937 enter the fault management mode.
When the power MOSFET is fully enhanced, the
MAX5936/MAX5937 monitor the drain voltage (V_OUT) for
circuit-breaker and short-circuit faults. The MAX5936/
MAX5937 make use of the power MOSFET’s R_DS(ON) as
the current-sense resistance to detect excessive current
through the load. The short-circuit threshold voltage,
V_SC, is twice V_CB (V_SC = 2 x V_CB) and is available in
100mV, 200mV, and 400mV thresholds. V_CB and V_SC
are temperature-compensated (increasing with tempera-
ture) to track the normalized temperature coefficient of
R_DS(ON) for typical power MOSFETs.
When the load current is increased during full enhance-
ment, this causes V_OUT to exceed V_CB but remains less
than V_SC, and starts the 1.2ms circuit-breaker glitch
rejection timer. At the end of the glitch rejection period,
if V_OUT still exceeds V_CB, the GATE is immediately
pulled to V_EE (330ns), PGOOD (PGOOD) is deasserted,
and the part enters fault management. Alternatively,
during full enhancement when V_OUT exceeds V_SC,
there is no glitch rejection timer. GATE is immediately
pulled to V_EE, PGOOD is deasserted, and the part
enters fault management.
V_IN
50V/div
V_GATE
10V/div
V_OUT
50V/div
V_PGOOD
50V/div
V_IN
50V/div
V_GATE
10V/div
V_OUT
50V/div
V_PGOOD
50V/div
40ms/div
I_IN
2A/div
40ms/div
I_IN
2A/div
Figure 4. MAX5936 Normal Condition
Figure 5. MAX5936 Startup in Fault Condition
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