MAX3638 Datasheet, PDF (9/22 Pages) Maxim Integrated Products – Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs

Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
PIN
1
2
3
4
5
6
7, 8
9
10
11
12
13, 14
15, 16
17, 18
19
20
21
22, 23
24
25, 36
26, 27
28, 29
30, 31
32, 33
34, 35
37
38, 39
40, 41
42, 43
44
45
46, 47
48
—
NAME
DM
XIN
XOUT
VCC
IN_SEL
PLL_BP
DF1, DF0
QC_CTRL
VCCA
RES
DP
DB1, DB0
DA1, DA0
DC1, DC0
QA_CTRL2
VCCQCC
QCC
QC, QC
VCCQC
VCCQA
QA4, QA4
QA3, QA3
QA2, QA2
QA1, QA1
QA0, QA0
VCCQB
QB0, QB0
QB1, QB1
QB2, QB2
QA_CTRL1
QB_CTRL
DIN, DIN
CIN
EP
Pin Description
FUNCTION
LVCMOS/LVTTL Input. Three-level control for input divider M. See Table 3.
Crystal Oscillator Input
Crystal Oscillator Output
Core Power Supply. Connect to +3.3V.
LVCMOS/LVTTL Input. Three-level control for input mux. See Table 1.
LVCMOS/LVTTL Input. Three-level control for PLL bypass mode. See Table 2.
LVCMOS/LVTTL Inputs. Three-level controls for feedback divider F. See Table 4.
LVCMOS/LVTTL Input. Three-level control input for C-bank output interface. See Table 10.
Power Supply for Internal Voltage-Controlled Oscillators (VCOs). See Figure 3.
Reserved. Connect to GND for normal operation.
LVCMOS/LVTTL Input. Three-level control for prescale divider P. See Table 7.
LVCMOS/LVTTL Inputs. Three-level controls for output divider B. See Table 5.
LVCMOS/LVTTL Inputs. Three-level controls for output divider A. See Table 5.
LVCMOS/LVTTL Inputs. Three-level controls for output divider C. See Table 6.
LVCMOS/LVTTL Input. Three-level control for QA[4:3] output interface. See Table 8.
Power Supply for QCC Output. Connect to +3.3V.
C-Bank LVCMOS Clock Output
C-Bank Differential Output. Configured as LVPECL or LVDS with the QC_CTRL pin.
Power Supply for C-Bank Differential Output. Connect to +3.3V.
Power Supply for A-Bank Differential Outputs. Connect to +3.3V.
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL2 pin.
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL2 pin.
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin.
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin.
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin.
Power Supply for B-Bank Differential Outputs. Connect to +3.3V.
B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin.
B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin.
B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin.
LVCMOS/LVTTL Input. Three-level control for QA[2:0] output interface. See Table 8.
LVCMOS/LVTTL Input. Three-level control for B-bank output interface. See Table 9.
Differential Clock Input. Operates up to 350MHz. This input can accept DC-coupled LVPECL sig-
nals, and is internally biased to accept AC-coupled LVDS, CML, and LVPECL signals.
LVCMOS Clock Input. Operates up to 160MHz.
Exposed Pad. Connect to supply ground for proper electrical and thermal performance.
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