MAX3624_0711 Datasheet, PDF (9/13 Pages) Maxim Integrated Products – Low-Jitter, Precision Clock Generator with Four Outputs

Low-Jitter, Precision Clock Generator
with Four Outputs
PLL Divider Configuration
Table 3 shows the input settings required to set PLL
feedback divider.
Crystal Selection
The crystal oscillator is designed to drive a fundamen-
tal mode, AT-cut crystal resonator. See Table 4 for rec-
ommended crystal specifications. See Figure 4 for
external capacitance connection.
Table 3. PLL Divider Configuration Chart
FB_SEL1
0
0
1
1
INPUT
FB_SEL0
0
1
0
1
M DIVIDER
÷25
÷24
÷32
÷16
Table 4. Crystal Selection Parameters
PARAMETER
Crystal Oscillation Frequency
Shunt Capacitance
Load Capacitance
Equivalent Series Resistance
(ESR)
SYMBOL MIN TYP
f_OSC
19.375
C_O
2.0
C_L
18
R_S
Maximum Crystal Drive Level
Crystal Input Layout and Frequency
Stability
The crystal, trace, and two external capacitors should
be placed on the board as close as possible to the
MAX3624’s X_IN and X_OUT pins to reduce crosstalk
of active signals into the oscillator.
The layout shown in Figure 3 gives approximately 3pF
of trace plus footprint capacitors per side of the crystal
(Y1). The dielectric material is FR-4 and dielectric thick-
ness of the reference board is 15 mils. Using a 25MHz
crystal and the capacitor values of C22 = 27pF and
C23 = 33pF, the measured output frequency accuracy
is -14ppm at +25°C ambient temperature.
MAX
27
7.0
50
300
UNITS
MHz
pF
pF
Ω
µW
27pF
CRYSTAL
(C_L = 18pF)
33pF
X_IN
X_OUT
Figure 4. Crystal, Capacitors Connection
Figure 3. Crystal Layout
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