MAX16056 Datasheet, PDF (9/17 Pages) Maxim Integrated Products – 125nA Supervisory Circuits with Capacitor- Adjustable Reset and Watchdog Timeouts

MAX16056–MAX16059
125nA Supervisory Circuits with Capacitor-
Adjustable Reset and Watchdog Timeouts
Applications Information
Selecting the Reset Timeout Capacitor
The reset timeout period is adjustable to accommodate
a variety of µP applications. To adjust the reset timeout
period (t_RP), connect a capacitor (C_SRT) between SRT
and ground. The reset timeout capacitor is calculated
as follows:
C_SRT = t_RP/(5.15 x 10⁶)
with t_RP in seconds and C_SRT in Farads.
C_SRT must be a low-leakage (< 10nA) type capacitor. A
ceramic capacitor with low temperature coefficient
dielectric (i.e., X7R) is recommended.
Selecting Watchdog Timeout Capacitor
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer can determine how often
the watchdog timer should be serviced. Adjust the
watchdog timeout period (t_WD) by connecting a capaci-
tor (C_SWT) between SWT and GND. For normal mode
operation, calculate the watchdog timeout as follows:
t_WD = Floor[C_SWT x 5.15 x 10⁶/6.4ms] x 6.4ms + 3.2ms
with t_WD in seconds and C_SWT in Farads.
(Floor: take the integral value) (Figures 2 and 3)
The maximum t_WD is 296s. If the capacitor sets t_WD
greater than the 296s, t_WD = infinite and the watchdog
timer is disabled.
C_SWT must be a low-leakage (< 10nA) type capacitor.
A ceramic capacitor with low temperature coefficient
dielectric (i.e., X7R) is recommended.
Watchdog Timeout Accuracy
The watchdog timeout period is affected by the SWT
ramp current (I_RAMP2) accuracy, the SWT ramp thresh-
old (V_RAMP2) and the watchdog timeout clock period
(t_WDPER). In the equation above, the constant 5.15 x
10⁶ is equal to V_RAMP2/I_RAMP2, and 6.4ms equals the
watchdog timeout clock period. Calculate the timeout
accuracy by substituting the minimum, typical, and
maximum values into the equation.
For example, if C_SWT = 100nF.
t_WDMIN = Floor[100 x 10^-9 x 1.173/(282 x 10^-9)/9.5ms] x
3.5ms + 0.5 x 3.2ms = 141.7ms
t_WDNOM = Floor[100 x 10^-9 x 1.235/(240 x 10^-9)/6.4ms]
x 6.4ms + 0.5 x 6.4ms = 515.2ms
t_WDMAX = Floor[100 x 10^-9 x 1.297/(197 x 10^-9)/3.5ms]
x 9.5ms + 0.5 x 9.5ms = 1790.75ms
Transient Immunity
For applications with higher slew rates on V_CC during
power-up, additional bypass capacitance may be
required.
The MAX16056–MAX16059 are relatively immune to
short-duration supply voltage transients, or glitches on
V_CC. The Maximum V_CC Transient Duration vs. Reset
Threshold Overdrive graph in the Typical Operating
Characteristics shows this transient immunity. The area
below the curve of the graph is the region where these
devices typically do not generate a reset pulse. This
graph was generated using a falling pulse applied to
V_CC, starting 100mV above the actual reset threshold
(V_TH) and ending below this threshold (reset threshold
overdrive). As the magnitude of the transient increases,
the maximum allowable pulse width decreases.
Typically, a 100mV V_CC transient duration of 40µs or
less does not cause a reset.
Using the MAX16056–MAX16059 for
Reducing System Power Consumption
Using the RESET output to control an external p-channel
MOSFET to control the on-time of a power supply can
result in lower system power consumption in systems that
can be regularly put to sleep. By tying the WDI input to
ground, the RESET output becomes a low-frequency
clock output. When RESET is low, the MOSFET is turned
on and power is applied to the system. When RESET is
high, the MOSFET is turned off and no power is con-
sumed by the system. This effectively reduces the shut-
down current of the system to zero (Figure 4).
Maxim Integrated
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