MAX16010_08 Datasheet, PDF (9/12 Pages) Maxim Integrated Products – Ultra-Small, Overvoltage Protection/Detection Circuits

Ultra-Small, Overvoltage Protection/
Detection Circuits
In normal operating mode, internal GATE1 output cir-
cuitry enhances P1 to a 10V gate-to-source (V_GS) for
11V < V_CC < 72V. The constant 10V enhancement
ensures P1 operates in a low R_DS-ON mode, but the
gate-source junction is not overstressed during high-
battery-voltage application or transients (many MOSFET
devices specify a ±20V V_GS absolute maximum). As
V_CC drops below 10V GATE1 is limited to GND, reduc-
ing P1 V_GS to V_CC - GND. In normal operation the P1
power dissipation is very low:
P1 = I_LOAD² x R_DS-ON
During reverse-battery applications, GATE1 is limited to
GND and the P1 gate-source junction is reverse
biased. P1 is turned off and neither the MAX16013/
MAX16014 nor the load circuitry is exposed to the
reverse-battery voltage. Care should be taken to place
P1 (and its internal drain-to-source diode) in the correct
orientation for proper reverse battery operation.
P2 protects the load from input overvoltage conditions.
During normal operating modes (the monitored voltage
is below the adjusted overvoltage threshold), internal
GATE2 output circuitry enhances P2 to a 10V gate-to-
source (V_GS) for 11V < V_CC < 72V. The constant 10V
enhancement ensures P2 operates in a low R_DS-ON
mode but the gate-to-source junction is not over-
stressed during high-battery-voltage applications
(many pFET devices specify a ±20V V_GS absolute max-
imum). As V_CC drops below 10V, GATE2 is limited to
GND, reducing P2 V_GS to V_CC - GND. In normal opera-
tion, the P2 power dissipation is very low:
P2 = I_LOAD² x R_DS-ON
During overvoltage conditions, P2 is either turned com-
pletely off (overvoltage-switch mode) or cycled off-on-
off (voltage-limiter mode). Care should be taken to
place P2 (and its internal drain-to-source diode) in the
correct orientation for proper overvoltage protection
operation. During voltage-limiter mode, the drain of P2
is limited to the adjusted overvoltage threshold, while
the battery (V_CC) voltage rises. During prolonged over-
voltage events, P2 temperature can increase rapidly
due to the high power dissipation. The power dissipat-
ed by P2 is:
P2 = V_DS-P2 x I_LOAD
= (V_CC - V_OV-ADJUSTED) x I_LOAD
where V_CC ~ V_BATTERY and V_OV-ADJUSTED is the desired
load limit voltage. For prolonged overvoltage events with
high P2 power dissipation, proper heatsinking is required.
Adding External Pullup Resistors
It may be necessary to add an external resistor from
V_CC to GATE1 to provide enough additional pullup
capability when the GATE1 input goes high. The
GATE_ output can only source up to 1µA current. If the
source current is less than 1µA, no external resistor
may be necessary. However, to improve the pullup
capability of the GATE_ output when it goes high, con-
nect an external resistor between V_CC and the GATE_.
The application shows a 2MΩ resistor, which is large
enough not to impact the sinking capability of the
GATE_ (during normal operation) while providing
enough pullup during an overvoltage event. With an
11V (worst case) V_CC-to-gate clamp voltage and a
sinking current of 75µA, the smallest resistor should be
11V/75µA, or about 147kΩ. However, since the GATE_
is typically low most of the time, a higher value should
be used to reduce overall power consumption.
_______________________________________________________________________________________ 9