MAX15024_10 Datasheet, PDF (9/16 Pages) Maxim Integrated Products – Single/Dual, 16ns, High Sink/source Current Gate Drivers

Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Pin Description
MAX15024
PIN
MAX15025A MAX15025C
MAX15025B MAX15025D
1
1
1
NAME
FB/SET
FUNCTION
LDO Regulator Output Set. Feedback for V_REG adjustment (V_FB > 200mV).
Connect FB/SET to GND for a fixed 10V output REG. Connect FB/SET to a
resistor ladder to set V_REG.
2
2
3
3
4
—
—
4
5
—
—
5
—
—
6
6
7
—
—
7
8
—
—
8
9
9
Power-Supply Input. Bypass to GND with a low-ESR ceramic capacitor of
2
V_CC 1µF. Input of the internal housekeeping regulator and of the main REG
regulator.
3
GND Signal Ground
—
IN+ Driver Noninverting Logic Input. Connect to V_CC when not used.
4
IN1 Driver 1 Noninverting Logic Input
—
IN- Driver Inverting Logic Input. Connect to GND when not used.
—
IN2 Driver 2 Noninverting Logic Input
5
IN2 Driver 2 Inverting Logic Input
6
PGND ^{Power Ground. Sink current return. Source of the internal pulldown}
n-channel transistor.
—
N_OUT ^{Sink Output. Open-drain n-channel output. N_OUT sinks current for power}
MOSFET turn-off.
7
OUT2 Driver 2 Output
—
P_OUT
Source Output. Pullup p-channel output (open drain). Sources current for
power MOSFET turn-on.
8
OUT1 Driver 1 Output
Output Driver Supply Voltage. Decouple DRV with a low ESR > 0.1µF
ceramic capacitor to PGND placed in close proximity to the device. DRV
9
DRV can be powered independently from REG. Connect DRV, REG, and V_CC
together when there is no need for special DRV supply sequencing and
the power-MOSFET gate voltage does not need to be regulated or limited.
Voltage Regulator Output. Connect to DRV for driving the power MOSFET
10
10
10
REG
with regulated V_GS amplitude. Bypass with a low-ESR 1µF (minimum)
ceramic capacitor to GND placed in close proximity to the device to
ensure regulator stability.
—
—
Exposed Pad. Internally connected to GND. Connect to GND plane or
—
EP thermal pad and use multiple vias to a solid copper area on the bottom of
the PCB.
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