MAX1294 Datasheet, PDF (9/20 Pages) Maxim Integrated Products – 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADCs’ analog com-
parator is illustrated in the equivalent input circuits of
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1294
(Figure 3a) and to CH0–CH1 for the MAX1296 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
the analog inputs. This configuration is pseudo-differen-
tial to the effect that only the signal at IN+ is sampled.
The return side (IN-) must remain stable within ±0.5LSB
(±0.1LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
12-BIT CAPACITIVE DAC
V_REF
CH0
INPUT
MUX
C_HOLD
–+
COMPARATOR
ZERO
12pF
CH1
R_IN
CH2
C_SWITCH
800Ω
CH3
HOLD
CH4
TRACK
AT THE SAMPLING INSTANT,
CH5
T/H
SWITCH
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
COM
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3, AND CH4/CH5
Figure 3a. MAX1294 Simplified Input Structure
12-BIT CAPACITIVE DAC
V_REF
CH0
INPUT
MUX
C_HOLD
–+
COMPARATOR
ZERO
12pF
CH1
R_IN
C_SWITCH
800Ω
TRACK
HOLD
AT THE SAMPLING INSTANT,
T/H
SWITCH
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
COM
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1.
Figure 3b. MAX1296 Simplified Input Structure
Table 1. Control-Byte Functional Description
BIT
D7, D6
D5
D4
D3
D2, D1, D0
NAME
FUNCTIONAL DESCRIPTION
PD1 and PD0 select the various clock and power-down modes.
0
0
Full Power-Down Mode. Clock mode is unaffected.
PD1, PD0
0
1
Standby Power-Down Mode. Clock mode is unaffected.
1
0
Normal Operation Mode. Internal clock mode selected.
1
1
Normal Operation Mode. External clock mode selected.
ACQMOD
SGL/DIF
UNI/BIP
A2, A1, A0
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (see Tables 2, 4).
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V_REF can be converted; in bipolar mode, the
signal can range from -V_REF/2 to +V_REF/2.
Address bits A2, A1, A0 select which of the 6/2 (MAX1294/MAX1296) channels is to be converted
(see Tables 2, 3).
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