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MAX1277 Datasheet, PDF (9/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs with Internal Reference
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1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
PIN
1
2
3
4
5, 11
6
7
8
9
10
12
—
NAME
AIN-
REF
RGND
VDD
N.C.
GND
VL
DOUT
CNVST
SCLK
AIN+
EP
Pin Description
FUNCTION
Negative Analog Input
Reference Voltage Output. Internal 2.048V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.
No Connection
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
REF
AIN +
AIN -
VDD
REF
2.048V
TRACK AND
HOLD
12-BIT
SAR
ADC
VL
OUTPUT
BUFFER
DOUT
RGND
MAX1277
MAX1279
CONTROL
LOGIC AND
TIMING
CNVST
SCLK
GND
Figure 3. Functional Diagram
Detailed Description
The MAX1277/MAX1279 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1277/MAX1279.
CIN+ RIN+
AIN+
VAZ
COMP
AIN-
CIN- RIN- ACQUISITION MODE
CIN+ RIN+
AIN+
VAZ
COMP
AIN-
CIN- RIN-
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
CONTROL
LOGIC
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