DS8023 Datasheet, PDF (9/17 Pages) Maxim Integrated Products – Smart Card Interface

DS8023
Smart Card Interface
When a card is inserted into the reader (if PRES is
active), the host microcontroller can begin an activation
sequence (start a card session) by pulling CMDVCC
low. The following events form an activation sequence
(Figure 3):
1) Host: CMDVCC is pulled low.
2) DS8023: The internal oscillator changes to high
frequency (t₀).
3) DS8023: The voltage generator is started simulta-
neously (t₁ = t₀).
4) DS8023: Raise V_CC from 0 to 5V, 3V, or 1.8V with
a controlled slope (t₂ = t₁ + 1.5 × T). T is 64 times
the internal oscillator period (approximately 25µs).
5) DS8023: I/O, AUX1, and AUX2 are enabled
(t₃ = t₁ + 4T).
6) DS8023: The CLK signal is applied to the C3 con-
tact (t₄).
7) DS8023: RST is enabled simulataneously (t₅ = t₄ =
t₁₁ + 7T).
An alternate sequence allows the application to control
when the clock is applied to the card.
1) Host: Set RSTIN high.
2) Host: Set CMDVCC low.
3) Host: Set RSTIN low between t₃ and t₅; CLK will now
start.
4) DS8023: RST stays low until t₅, then RST becomes
the copy of RSTIN.
5) DS8023: RSTIN has no further effect on CLK after t₅.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK starts at t₃ (minimum
200ns after the transition on I/O, see Figure 4); after t₅,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform acti-
vation with RSTIN held permanently high.
CMDVCC
V_CC
I/O
CLK
RSTIN
RST
I/OIN
t₀ t₁
t₂
t₃
t₄
Figure 3. Activation Sequence Using RSTIN and CMDVCC
t₅ = t_ACT
Maxim Integrated
ATR
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