DS1673 Datasheet, PDF (9/18 Pages) Dallas Semiconductor – Portable System Controller

DS1673
WATCHDOG TIME-OUT CONTROL Figure 5
WATCHDOG REGISTER
BIT 7
BIT 6
BIT 5
0
0
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
TD1
BIT 0
TD0
WATCHDOG REGISTER
TD1
TD0
WATCHDOG TIME-OUT
0
0
WATCHDOG DISABLED
0
1
250 ms
1
0
500 ms
1
1
1000 ms
ANALOG-TO-DIGITAL CONVERTER
The DS1673 provides a 3-channel, 8-bit analog-to-digital converter. The ADC reference voltage (2.55V
typical) is derived from an on-chip band-gap circuit. Three multiplexed analog inputs are provided
through the AIN0, AIN1, and AIN2 pins. The ADC is monotonic (no missing codes) and uses a
successive approximation technique to convert the analog signal into a digital code.
An A/D conversion is the process of assigning a digital code to an analog input voltage. This code
represents the input value as a fraction of the full-scale voltage (FSV) range. Thus, the FSV range is then
divided by the ADC into 256 codes (8 bits). The FSV range is bounded by an upper limit equal to the
reference voltage and the lower limit, which is ground. The DS1673 has a FSV of 2.55V (typical) that
provides a resolution of 10mV. An input voltage equal to the reference voltage converts to FFh while an
input voltage equal to ground converts to 00h. The relative linearity of the ADC is ±0.5 LSB.
The A/D converter selects from one of three different analog inputs (AIN0–AIN2). The input that is
selected is determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists the
specific analog input that is selected by these 2 bits. Note also that the converter can be turned off by
these bits to reduce power. When the ADC is turned on by setting AIS0 and AIS1 to any value other than
0,0 the analog input voltage is converted and written to the ADC Register within 488ms. An internal
analog filter at the input reduces high frequency noise. Subsequent updates occur approximately every
10ms. If AIS0 and/or AIS1 are changed, updates will occur at the next 10 ms conversion time.
The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can
be read. When this bit is a 1, an update to the ADC Register will occur within 488ms maximum. However,
when this bit is 0 an update will not occur for at least 244ms. The CU bit should be polled before reading
the ADC Register to insure that the contents are stable during a read cycle. Once a read cycle to the ADC
Register has been started, the DS1673 will not update that register until the read cycle has been
completed. It should also be mentioned that taking CS low will abort the read cycle and will allow the
ADC Register to be updated.
Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the
completion of that conversion.
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