MAX4731 Datasheet, PDF (8/12 Pages) Maxim Integrated Products – 50 ΩDual SPST Analog Switches in UCSP

50Ω Dual SPST Analog Switches in UCSP
Power-Supply Sequencing and
Overvoltage Protection
CAUTION: Do not exceed the absolute maximum
ratings. Stresses beyond the listed ratings can
cause permanent damage to the devices.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current limited. If this sequencing is not possible, and if
the analog inputs are not current limited to <20mA, add
a small-signal diode, D1, as shown in Figure 1. If the
analog signal can dip below GND, add D2. Adding
protection diodes reduces the analog signal range to a
diode drop (about 0.7V) below V+ (for D1), and to a
diode drop above ground (for D2). Leakage is unaffect-
ed by adding the diodes. On-resistance increases
slightly at low supply voltages. Maximum supply volt-
age (V+) must not exceed +11V.
Adding protection diodes causes the logic thresholds to
be shifted relative to the power-supply rails. The most
significant shift occurs when using low supply voltages
(+5V or less). With a +5V supply, TTL compatibility is
not guaranteed when protection diodes are added.
Driving IN1 and IN2 all the way to the supply rails (i.e.,
to a diode drop higher than the V+ pin, or to a diode
drop lower than the GND pin) is always acceptable.
Protection diodes D1 and D2 also protect against some
overvoltage situations. Using the circuit in Figure 1, no
damage results if the supply voltage is below the
absolute maximum rating (+12V) and if a fault voltage
up to the absolute maximum rating (V+ + 0.3V) is
applied to an analog signal terminal.
UCSP Package Consideration
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note, “Wafer-Level Chip-Scale Packages.”
UCSP Reliability
The chip-scale package (UCSP) represents a unique
package that greatly reduces board space compared
to other packages. UCSP reliability is integrally linked
to the user’s assembly methods, circuit board material,
and usage environment. The user should closely review
these areas when considering a UCSP. Performance
through Operation Life Test and Moisture Resistance is
equal to conventional package technology as the
wafer-fabrication process primarily determines it.
However, this form factor may not perform equally to a
packaged product through traditional mechanical relia-
bility tests.
Mechanical stress performance is a greater considera-
tion for a UCSP. UCSP solder joint contact integrity
must be considered since the package is attached
through direct solder contact to the user’s PC board.
Testing done to characterize the UCSP reliability perfor-
mance shows that it is capable of performing reliably
through environmental stresses. Results of environmen-
tal stress test and additional usage data and recom-
mendations are detailed in the UCSP application note,
which can be found on Maxim’s website at
www.maxim-ic.com.
Test Circuits/Timing Diagrams
V+
EXTERNAL BLOCKING DIODE
D1
V+
*
NO_
*
*
COM_
*
MAX4731
MAX4732
MAX4733
GND
EXTERNAL BLOCKING DIODE
D2
GND
*INTERNAL PROTECTION DIODES.
Figure 1. Overvoltage Protection Using External Blocking Diodes
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