MAX3624A Datasheet, PDF (8/12 Pages) Maxim Integrated Products – Low-Jitter, Precision Clock Generator with Four Outputs

Low-Jitter, Precision Clock Generator
with Four Outputs
Table 1. Output Frequency Determination
XO OR CMOS
INPUT
FREQUENCY
(MHz)
FEEDBACK
DIVIDER, M
VCO
FREQUENCY
(MHz)
25
25
625
25.78125
26.04166
25
644.53125
24
625
26.5625
24
19.44
32
38.88
16
(CMOS input)
637.5
622.08
622.08
OUTPUT
DIVIDER,
NA AND NB
÷2
÷4
÷5
÷8
÷10
÷4
÷2
÷4
÷5
÷8
÷10
÷2
÷3
÷4
÷6
÷12
÷2
÷4
÷8
÷2
÷4
÷8
OUTPUT
FREQUENCY
(MHz)
312.5
156.25
125
78.125
62.5
161.132812
312.5
156.25
125
78.125
62.5
318.75
212.5
159.375
106.25
53.125
311.04
155.52
77.76
311.04
155.52
77.76
APPLICATIONS
Ethernet
10Gbps Ethernet
Ethernet
Fibre Channel
SONET/SDH
SONET/SDH
Output Divider Configuration
Table 2 shows the input settings required to set the out-
put dividers. Leakage in the open case must be less
than 1µA. Note that when the MAX3624A is in bypass
mode (BYPASS set low), the output dividers are auto-
matically set to divide by 1.
Table 2. Output Divider Configuration
INPUT
SELA1/SELB1
SELA0/SELB0
NA/NB DIVIDER
0
0
÷2*
0
1
÷3*
1
0
÷4
1
1
÷5
1
Open
÷6
Open
1
÷8
0
Open
÷10
Open
0
÷12
Open
Open
÷1*
*Maximum guaranteed output frequency is 160MHz for CMOS
and 320MHz for LVPECL output.
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