MAX3507 Datasheet, PDF (8/12 Pages) Maxim Integrated Products – Upstream CATV Amplifier with On-Chip Anti-Alias Filter

Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
word (D6–D0) programmed through the serial data
interface (Tables 1 and 2).
Equalizer Function
It is possible to add passband amplitude equalization
to the MAX3507. This is accomplished by adding pole-
zero peaking to the Gm stage of the PGA. Placing a
series RC network between pins EQ+ and EQ- realizes
the peaking function. Refer to Typical Operating
Characteristics for typical values and the associated
degree of equalization.
Power Amplifier
The power amplifier is a Class A differential amplifier
capable of driving +64dBmV (QPSK) differentially. This
architecture provides superior even-order distortion
performance but requires that a transformer be used to
convert to a single-ended output. In transmit-disable
mode, the output amplifier is shut off. Disabling the out-
put devices also allows the lowest standby noise.
To achieve the proper load line, the output impedance
of the power amplifier is 300Ω differential. To match the
output impedance to a 75Ω load, the transformer must
have a turns ratio (voltage ratio) of 2:1 (4:1 impedance
ratio). The differential amplifier is biased directly from
the +5V supply using the center tap of the output trans-
former. This provides a significant benefit when switch-
ing between transmit mode and transmit disable mode.
Stored energy due to bias currents will cancel within
the transformer and prevent switching transients from
reaching the load.
Serial Interface
The serial interface has an active-low enable (CS) to
bracket the data, with data clocked in MSB first on the
rising edge of SCLK. Data is stored in the storage latch
on the rising edge of CS. The serial interface controls
the gain state of the PGA and the output amplifier.
Tables 1 and 2 show the register format. Serial interface
timing is shown in Figure 1.
Applications Information
Transmit High-Power and Low-Noise Modes
The MAX3507 has two transmit modes, high-power
(HP) mode and low-noise (LN) mode. Each of these
modes is controlled by D7 (MSB) of the 8-bit program-
ming word. When D7 is a logical 1, HP mode is
enabled. When D7 is a logical 0, LN mode is enabled.
Each of these modes is characterized by the activation
of a distinct output stage. In HP mode, the output stage
exhibits a gain that is 15dB higher than gain in LN
mode. In LN mode, the lower gain output stage allows
Table 1. Serial-Interface Control Word
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
MNEMONIC
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
High-Power/Low-Noise Mode
Select
Gain Code, Bit 6
Gain Code, Bit 5
Gain Code, Bit 4
Gain Code, Bit 3
Gain Code, Bit 2
Gain Code, Bit 1
Gain Code, Bit 0
for significantly lower output noise and lower
transmit/transmit disable transients.
The full range of gain codes (D6–D0) may be used in
either mode. For DOCSIS applications, HP mode is rec-
ommended for output levels at or above +42dBmV, and
LN mode is recommended for output levels below
+42dBmV.
Shutdown Mode
In normal operation, the shutdown pin (SHDN) is held
high. When SHDN is set low, all circuits within the
device are disabled. Only leakage currents flow in this
state. Data stored within the serial data interface latch-
es will be lost upon entering this mode. Current con-
sumption is reduced to 1µA (typ) in shutdown mode.
Output Match
The MAX3507 output impedance is internally matched
to 300Ω. This 300Ω internal resistor is placed across
the OUT+ and OUT- terminals. When used in conjunc-
tion with a 2:1 (voltage ratio) transformer, the MAX3507
output impedance is matched to 75Ω.
To improve the output impedance matching for the high-
end frequency range (65MHz), a reactive match may be
employed as part of the ensuing diplex filter. The reac-
tive match normally consists of a series inductor (180nH
typ) followed by a shunt capacitor (33pF typ), and is
placed directly after the output transformer. This match
will also improve the gain flatness substantially.
As mentioned above, the matching components may be
incorporated into the diplex filter design. Optimize the
input impedance of the diplex filter to be 35 + j35 (typ)
at 65MHz when using the specified output transformer.
Transformer
To match the output of the MAX3507 to a 75Ω load, a
2:1 (voltage ratio) transformer is required. This trans-
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