MAX3272 Datasheet, PDF (8/14 Pages) Maxim Integrated Products – +3.3V, 2.5Gbps Low-Power Limiting Amplifier

+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
V_CC
50Ω
50Ω
ESD
STRUCTURES
OUT+
OUT-
GND LEVEL
Figure 5. CML Output Circuit
CML Output Buffer
The MAX3272/MAX3272A CML output circuit (Figure 5)
provides high tolerance to impedance mismatches and
inductive connectors. The output current can be set to
two levels using the LEVEL pin. When LEVEL is uncon-
nected, the output current is approximately 16mA.
Connecting LEVEL to ground sets the output current to
approximately 20mA. The squelch function is enabled
when the SQUELCH pin is set to a TTL high. This func-
tion holds OUT+ and OUT- to a static level whenever
the input signal amplitude drops below the loss-of-sig-
nal threshold. This circuit is also equipped with a polari-
ty selector, programmed by the OUTPOL pin. When
this pin is connected to V_CC, no inversion will occur.
When connected to ground, the output signal will be
inverted.
Design Procedure
Program the LOS Assert Threshold
External resistor R_TH programs the loss-of-signal
threshold. See the LOS Threshold vs. R_TH graph in the
the Typical Operating Characteristics section to select
the appropriate resistor.
Select the Coupling Capacitors
When AC-coupling, input and output coupling capaci-
tors (C_IN and C_OUT) should be selected to minimize the
receiver’s deterministic jitter. Jitter is decreased as the
input low-frequency cutoff (f_IN) is decreased:
f_IN = 1 / [2π(50)(C_IN)]
For ATM/SONET or other applications using scrambled
NRZ data, select (C_IN, C_OUT) ≥ 0.1µF, which provides
f_IN < 32kHz. For Fibre Channel, Gigabit Ethernet, or
other applications using 8B/10B data coding, select
(C_IN, C_OUT) ≥ 0.01µF, which provides f_IN < 320kHz.
Refer to application note HFAN-1.1: Choosing AC-
Coupling Capacitors.
Select the Offset-Correction
Capacitor
The capacitor between CAZ1 and CAZ2 determines the
time constant of the signal path DC offset-cancellation
loop. To maintain stability, it is important to keep a one-
decade separation between f_IN and the low-frequency
cutoff (f_OC) associated with the DC offset-cancellation
circuit. For ATM/SONET or other applications using
scrambled NRZ data, f_IN < 32kHz, so f_OCMAX <
3.2kHz. Therefore, C_AZ = 0.1µF (f_OC = 2kHz). For Fibre
Channel or Gigabit Ethernet applications, leave pins
CAZ1 and CAZ2 open.
Program the LOS Time Constant
External capacitor C_CLOS programs the LOS assert
and deassert times. When inputting data with many
consecutive identical digits (CIDs), a longer time con-
stant may be advantageous, so LOS does not flag
incorrectly. In this case, connect the CLOS pin to a
0.01µF capacitor to set the assert time in the range of
2µs to 100µs. For scrambled data where the mark den-
sity is kept at 50%, a shorter time constant may be
desirable. Leave the CLOS pin open for a shorter time
constant of about 1µs.
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