MAX14579E Datasheet, PDF (8/11 Pages) Maxim Integrated Products – Low-Power Headset Detectors with SEND/END Button Support Low-Power Microphone Mode

Low-Power Headset Detectors
with SEND/END Button Support
When microphone low-power mode (MPLP) is entered
by pulling the MODE input low, the bias voltage is dis-
connected from the RES output and is reconnected for a
short duration every 8ms (typ) to check for a SEND/END
button press event. MPLP is exited when the MODE input
transitions to logic-high.
Note that VBIAS is permanently disconnected from RES
when no jack is inserted and microphone low-power
mode is not entered.
Jack Insertion Detection
The MAX14579E/MAX14579AE detect jack insertion/
removal events by monitoring the DETIN input. Debounce
circuitry ensures that transient voltages do not force the
device to enter or exit MPLP due to false jack insertion/
removal detection.
MAX14579E Detection
The MAX14579E/MAX14579AEs' DETIN input has an
internal 1MI pullup resistor to VCC. DETIN monitors
a normally open insertion detection switch connected
between DETIN and an audio line. DETIN is pulled high
by the resistor, and DET is logic-high when no jack is
inserted into the socket. DETIN is pulled low by the
switch, and DET is logic-low when a jack is inserted.
Ensure that the total capacitance on DETIN is less than
100pF.
SEND/END Button Press Detection
The MAX14579E/MAX14579AE detect SEND/END but-
ton press events by monitoring the MIC input. A SEND/
END button press is detected if the voltage at MIC falls
below the MIC SEND/END detection threshold (0.22 O
VBIAS (typ)) for longer than the debounce time (typ). The
SWD output is logic-low for the duration of the SEND/
END button press event following the debounce period.
The SEND/END detection circuitry is active whenever a
jack is inserted.
The debounce period built into the SEND/END button
press detection allows the mechanical SEND/END but-
ton to reach steady-state before applying the micro-
phone bias. This mitigates click-and-pop noise.
MODE Control Input
An external host processor controls the MODE input.
Table 1 shows the behavior of the device based on
the MODE input and jack insertion status. The device
enters call mode when MODE is logic-high and a jack
is detected, enabling the LDO immediately in low-noise
mode (LNM). The 2.2V (typ) LDO output powers VBIAS
and is connected to the microphone through an external
2.2kI bias resistor.
Pull MODE low to put the device in standby mode. In
standby mode, VCC powers VBIAS, the LDO enters shut-
down mode (SDM), and the microphone bias connection
either turns off permanently if no jack is inserted or enters
MPLP if a jack is inserted.
The MODE input is compatible with 1.8V logic with VCC
voltages up to 5.5V.
Applications Information
Typical Connections for 3.5mm Jacks
There are two typical 3.5mm jacks: tip-ring-ring-sleeve
(TRRS) with four conductors (Figure 1a) and tip-ring-
sleeve (TRS) with three conductors (Figure 1b). The most
common configuration of the TRRS jack is to use rings 1
and 2 for audio signals, ring 3 for ground, and ring 4 for
a microphone. The TRS jack typically uses rings 1 and 2
for audio signals and rings 3 and 4 as ground.
Table 1. Operating Modes
MODE
DETIN/MIC
INSERTED
LDO Mode
MIC Bias Mode
LOW
LOW HIGH
SDM
MPLP
Off
HIGH
LOW
HIGH
SDM
2.2kI
Off
12 3 4
(a)
12 3 4
(b)
Figure 1. Typical 3.5mm Jacks
8   _______________________________________________________________________________________