MAX1274 Datasheet, PDF (8/18 Pages) Maxim Integrated Products – 1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs

1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Typical Operating Characteristics (continued)
(V_DD = +5V, V_L = V_DD, V_REF = 4.096V, f_SCLK = 28.8MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are measured
at T_A = +25°C)
V_L SUPPLY CURRENT
vs. TEMPERATURE
1.0
V_L SUPPLY CURRENT
vs. CONVERSION RATE
1.0
CONVERTING
0.8
f_SCLK = 28.8MHz
0.6
0.4
FULL/PARTIAL
POWER-DOWN
f_SCLK = 28.8MHz
0.2
0.8
V_L = 5V
0.5
V_L = 3V ^{VL = 1.8V}
0.3
0
-40 -15 10
35
60
85
TEMPERATURE (°C)
0
0
500
1000
1500
2000
f_SAMPLE (kHz)
PIN
1
2
3
4
5, 11
6
7
8
9
10
12
—
NAME
AIN-
REF
RGND
V_DD
N.C.
GND
V_L
DOUT
CNVST
SCLK
AIN+
EP
Pin Description
FUNCTION
Negative Analog Input
External Reference Voltage Input. V_REF sets the analog input range. Bypass REF with a 0.01µF
capacitor and a 4.7µF capacitor to RGND.
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+4.75V to +5.25V). Bypass V_DD with a 0.01µF capacitor and a 10µF
capacitor to GND.
No Connection
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to V_DD). Bypass V_L with a 0.01µF capacitor and a 10µF capacitor
to GND.
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
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