MAX1220_10 Datasheet, PDF(8/43 Page) Maxim Integrated Products – 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

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MAX1220_10 Datasheet, PDF (8/43 Pages) Maxim Integrated Products – 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

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12-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

ELECTRICAL CHARACTERISTICS (continued)

(AVDD = DVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), AVDD = 4.75V to 5.25V, DVDD = 2.7V to AVDD

(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40Â°C to +85Â°C,

unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1257), AVDD = DVDD = 5V (MAX1220/MAX1258), TA = +25Â°C.

Outputs are unloaded, unless otherwise noted.)

Note 1: Tested at DVDD = AVDD = +2.7V (MAX1257), DVDD = 2.7V, AVDD = +5.25V (MAX1220/MAX1258).

Note 2: Offset nulled.

Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the

clock period.

Note 4: See Table 5 for reference-mode details.

Note 5: Not production tested. Guaranteed by design.

Note 6: See the ADC/DAC References section.

Note 7: Fast automated test, excludes self-heating effects.

Note 8: Specified over the -40Â°C to +85Â°C temperature range.

Note 9: REFSEL[1:0] = 00 or when DACs are not powered up.

Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.

Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.

Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.

Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.

Note 15: All digital inputs at either DVDD or DGND. DVDD should not exceed AVDD.

Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.

Note 17: Clock mode 11 only.

Note 18: First conversion after reference power-up is always timed as if the internal reference was initially off to ensure the internal

reference has settled. Subsequent conversions are timed as shown.

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