MAX1178 Datasheet, PDF (8/14 Pages) Maxim Integrated Products – 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range

16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
CS
R/C
EOC
HBEN
D7/D15–D0/D8
t_CSL
t_CSH
t_ACQ
REF POWER-
DOWN CONTROL
t_DH
t_DS
t_CONV
HIGH-Z
t_DV
t_EOC
t_DO
t_DO
t_DO1
HIGH/LOW
BYTE VALID
t_BR
HIGH/LOW
BYTE VALID
HIGH-Z
Figure 2. MAX1178/MAX1188 Timing Diagram
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1178/MAX1188 automatically enter either standby
mode (reference and buffer on) or shutdown (reference
and buffer off) after each conversion, depending on the
status of R/C during the second falling edge of CS.
Internal Clock
The MAX1178/MAX1188 generate an internal conver-
sion clock to free the µP from the burden of running the
SAR conversion clock. Total conversion time (t_CONV)
after entering hold mode (second falling edge of CS) to
end-of-conversion (EOC) falling is 4.7µs (max).
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1178/MAX1188 (Figure 2). The first falling edge of
CS powers up the device and puts it in acquire mode if
R/C is low. The convert start is ignored if R/C is high.
The MAX1178/MAX1188 need at least 12ms for the
internal reference to wake up and settle before starting
the conversion (C_REFADJ = 0.1µF, C_REF = 10µF), if
powering up from shutdown.
+5V ANALOG +5V DIGITAL
0.1µF
0.1µF
ANALOG INPUT
AV_DD
AIN
DV_DD
D0–D7
OR
D8–D15
µP DATA
BUS
HIGH
BYTE
LOW
BYTE
R/C
CS
HBEN
MAX1178
MAX1188 EOC
REF
REFADJ
AGND DGND
0.1µF 10µF
Figure 3. Typical Operating Circuit for the MAX1178/MAX1188
8 _______________________________________________________________________________________