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MAX11129 Datasheet, PDF (8/36 Pages) Maxim Integrated Products – 3Msps, Low-Power, Serial 12-/10-Bit, 8-/16-Channel ADCs
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11129/MAX11130) (continued)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 3Msps, fSCLK = 48MHz, 50% duty cycle, VREF+ = VDD, TA= -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS (Figure 1) (Note 10)
SCLK Clock Period
tCP Externally clocked conversion
SCLK Duty Cycle
SCLK Fall to DOUT Transition
16th SCLK Fall to DOUT Disable
tCH
tDOT
tDOD
CLOAD =
10pF
VOVDD = 1.5V to 2.35V
VOVDD = 2.35V to 3.6V
CLOAD = 10pF, channel ID on
14th SCLK Fall to DOUT Disable
CLOAD = 10pF, channel ID off
SCLK Fall to DOUT Enable
tDOE CLOAD = 10pF
DIN to SCLK Rise Setup
tDS
SCLK Rise to DIN Hold
tDH
CS Fall to SCLK Fall Setup
tCSS
SCLK Fall to CS Fall Hold
tCSH
CNVST Pulse Width
tCSW See Figure 6
CS or CNVST Rise to EOC Low
(Note 7)
tCNV_INT See Figure 7, fSAMPLE = 3Msps
CS Pulse Width
tCSBW
MIN
20.8
40
4
4
4
1
4
1
5
5
TYP
2.1
MAX
UNITS
ns
60
%
16.5
ns
15
15
ns
16
14
ns
ns
ns
ns
ns
ns
2.4
Fs
ns
Note 2: Limits are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design.
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection D(DOUT) with VDD = 2.35V to 3.6V and VREF+ = 2.35V.
Note 7: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Note 8:
Note 9:
Maximum conversion time: 1.91Fs + N x 16 x TOSC_MAX
TOSC_MAX = 29.4ns, TOSC_TYP = 25ns.
The operational input voltage range for each individual input of a differentially configured pair is from VDD to GND. The
operational input voltage difference is from -VREF+/2 to +VREF+/2 or -VREF+ to +VREF+.
See Figure 3 (Equivalent Input Circuit).
Note 10: Guaranteed by characterization.
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