MAX1065_09 Datasheet, PDF (8/14 Pages) Maxim Integrated Products – Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface

Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
Detailed Description
Converter Operation
The MAX1065/MAX1066 use a successive-approximation
(SAR) conversion technique with an inherent track-and-
hold (T/H) stage to convert an analog input into a 14-bit
digital output. Parallel outputs provide a high-speed inter-
face to most microprocessors (µPs). The Functional
Diagram shows a simplified internal architecture of the
MAX1065/MAX1066. Figure 3 shows a typical application
circuit for the MAX1066.
DV_DD
D0–D13
1mA
D0–D13
1mA
C_LOAD = 20pF
C_LOAD = 20pF
DGND
DGND
a) HIGH-Z TO V_OH,
V_OL TO V_OH, AND
V_OH TO HIGH-Z
b) HIGH-Z TO V_OL,
V_OH TO V_OL, AND
V_OL TO HIGH-Z
Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13
Delay Time and Bus Relinquish Time
Analog Input
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent track-and-hold function. The sin-
gle-ended input is connected between AIN and AGND.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Internal protection diodes, which clamp the analog
input to AV_DD and/or AGND, allow the input to swing
from AGND - 0.3V to AV_DD + 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
Track and Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
CS
R/C
EOC
D0–D13
t_CSL
t_CSH
t_ACQ
REF POWER-
DOWN BIT
t_DH
t_DS
HI–Z
t_CONV
t_DV
t_DO
t_EOC
t_BR
HI-Z
DATA VALID
HBEN*
D7/D13–D0/D8*
t_DO1
HIGH/LOW
BYTE VALID
t_BR
HIGH/LOW
BYTE VALID
*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.
Figure 2. MAX1065/MAX1066 Timing Diagram
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