DG441 Datasheet, PDF (8/9 Pages) Intersil Corporation – Monolithic, Quad SPST, CMOS Analog Switches

Improved, Quad, SPST Analog Switches
Timing Diagrams/
Test Circuits (continued)
10nF ^+15V
D
+V
CAPACITANCE
METER
f = 1MHz
S
GND
IN
0.8V or 2.4V
V-
10nF
-15V
Figure 6. Source/Drain-On/Off Capacitance
Ordering Information (continued)
PART
TEMP RANGE
PIN-PACKAGE
DG441DK
-40°C to +85°C
16 CERDIP
DG441ETE
-40°C to +85°C
16 Thin QFN-EP**
DG441AK
-55°C to +125°C 16 CERDIP***
DG441MY/PR
-55°C to +125°C 16 Narrow SO
DG442CJ
0°C to +70°C
16 Plastic DIP
DG442CY
0°C to +70°C
16 Narrow SO
DG442C/D
0°C to +70°C
Dice*
DG442DJ
-40°C to +85°C
16 Plastic DIP
DG442DY
-40°C to +85°C
16 Narrow SO
DG442DK
-40°C to +85°C
16 CERDIP
DG442ETE
-40°C to +85°C
16 Thin QFN-EP**
DG442AK
-55°C to +125°C 16 CERDIP***
DG442MY/PR
-55°C to +125°C 16 Narrow SO
Note: Devices are available in both leaded and lead(Pb)-free
packaging. Specify lead-free by adding the + symbol at the
end of the part number when ordering.
*Contact factory for dice specifications.
**EP = Exposed pad.
***Contact factory for availability and processing to MIL-STD-
883B. Not available in lead-free.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
16 Plastic DIP
16 Narrow SO
16 CERDIP
16 Thin QFN-EP (5mm x 5mm)
PACKAGE CODE
P16-1
S16-3
J16-3
T1655-2
DOCUMENT NO.
21-0043
21-0041
21-0045
21-0140
8 _______________________________________________________________________________________