MAX5712 Datasheet, PDF (7/9 Pages) Maxim Integrated Products – 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23

12-Bit, Low-Power, Rail-to-Rail
Voltage-Output Serial DAC in SOT23
Detailed Description
The MAX5712 voltage output, 12-bit DAC, offers a full
12-bit performance in a small 6-pin SOT23 package.
The SOT23 footprint is less than 9mm². The MAX5712
has less than 1LSB differential nonlinearity error, ensur-
ing monotonic performance. The device uses a simple
3-wire, SPI/QSPI/MICROWIRE and DSP-compatible ser-
ial interface that operates up to 20MHz. The MAX5712
incorporates three shutdown modes, making it ideal for
low-power.
Analog Section
The MAX5712 consists of a resistor string, an output
buffer, and a POR circuit. Monotonic digital to analog
conversion is achieved using a resistor string architec-
ture. Since V_DD is the reference for the MAX5712, the
accuracy of the DAC depends on the accuracy of V_DD.
The low bias current of the MAX5712 allows its power
to be supplied by a voltage reference such as the
MAX6030. The 12-bit DAC code is binary-unipolar with
1LSB = V_DD/4096.
Output Buffer
The DAC output buffer has a rail-to-rail output and is
capable of driving a 5kΩ resistive load in parallel with a
200pF capacitive load. With a capacitive load of 200pF,
the output buffer slews 0.5V/µs. With a 1/4FS to 3/4FS
output transition, the amplifier output settles to 1/2LSB
in less than 10µs when loaded with 5kΩ in parallel with
200pF. The buffer amplifier is stable with any combina-
tion of resistive loads greater than 5kΩ and capacitive
loads less than 200pF.
Program the input register bits to power-down the
device. The DAC registers are preserved during power-
down and upon wake-up, the DAC output is restored to
its pre-power-down voltage.
Power-On Reset
The MAX5712 has a POR circuit to set the DACs output
to zero when V_DD is first applied. This ensures that
unwanted DAC output voltages will not occur immedi-
ately following a system start-up, such as after a loss of
power. Upon initial power-up, an internal power-on-
reset circuit ensures that all DAC registers are cleared,
the DAC is powered-down, and its output is terminated
to GND by a 100kΩ resistor. An 8µs recovery time after
issuing a wake-up command is needed before writing
to the DAC registers.
Digital Section
3-Wire Serial Interface
The MAX5712 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE/DSP
interfaces. The chip-select input (CS) frames the serial
data loading at DIN. Immediately following CS high-to-
low transition, the data is shifted synchronously and
latched into the input register on the falling edge of the
serial clock input (SCLK). After 16 bits have been
loaded into the serial input register, it transfers its con-
tents to the DAC latch. CS may then either be held low
or brought high. CS must be brought high for a mini-
mum of 80ns before the next write sequence, since a
write sequence is initiated on a falling edge of CS. Not
keeping CS low during the first 15 SCLK cycles dis-
cards input data. The serial clock (SCLK) can idle
either high or low between transitions. Figure 1 shows
the complete 3-wire serial interface transmission. Table
1 lists serial-interface mapping.
t_CH
t_CL
t_CSW
t_CSS
t_DH
t_CSH
t_DS
C3
SO
Figure 1. Timing Diagram
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