MAX5590_04 Datasheet, PDF (7/33 Pages) Maxim Integrated Products – Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD = 1.8V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SCLK Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Setup
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Rise to DOUTDC1 Valid
Propagation Delay
SYMBOL
f_SCLK
t_CH
t_CL
t_CSS
t_CSH
t_CS0
t_DS
t_DH
CONDITIONS
1.8V < DV_DD < 5.25V
(Note 7)
(Note 7)
t_DO1 C_L = 20pF, UPIO_ = DOUTDC1 mode
MIN TYP
40
40
20
0
10
20
5
SCLK Fall to DOUT_ Valid
Propagation Delay
t_DO2
C_L = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
CS Rise to SCLK Rise Hold Time
t_CS1 MICROWIRE and SPI modes 0 and 3
20
CS Pulse-Width High
t_CSW
90
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
t_DOZ
C_L = 20pF, from end of write cycle to UPIO_
in high impedance
DOUTRB Tri-State Time from CS
Rise
t_DRBZ
C_L = 20pF, from rising edge of CS to UPIO_
in high impedance
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low
LDAC Effective Delay
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
GPO Output High-Impedance
Time
t_ZEN
C_L = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
t_LDL
Figure 5
40
t_LDS Figure 6
200
t_CMS Figure 5
40
t_GP
Figure 6
t_GPZ
MAX
10
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
60
ns
60
ns
ns
ns
200
ns
40
ns
40
ns
ns
ns
ns
200
ns
200
ns
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