MAX2821ETM Datasheet, PDF (7/26 Pages) KOA Speer Electronics, Inc. – 2.4GHz 802.11b Zero-IF Transceivers

2.4GHz 802.11b Zero-IF Transceivers
AC ELECTRICAL CHARACTERISTICS—SYSTEM TIMING
(MAX2820/MAX2821 EV kit: V_CC = +2.7V to +3.6V, f_RF and f_LO = 2400MHz to 2499MHz, f_OSC = 22MHz or 44MHz, SHDNB = V_IH,
CSB = V_IH, RBIAS = 12kΩ, I_CP = +2mA, BW_LOOP = 45kHz, registers set to default power-up settings, T_A = +25°C, unless otherwise
noted. Typical values are at V_CC = +2.7V, f_LO = 2437MHz, f_OSC = 22MHz, unless otherwise noted.) (Note 11)
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Channel-Switching Time
f_LO = 2400MHz ↔ 2499MHz,
f_LO settles to ±10kHz (Note 9)
150
200
µs
RX/TX Turnaround Time
(Note 11)
RX to TX, output settles to within ±2dB of final value of
output power, relative to rising edge of TX_ON
TX to RX, output settles to within ±2dB of final value of
output power, relative to rising edge of RX_ON
3
µs
5
Standby-to-Transmit Mode
Standby to TX, output settles to within ±2dB of final value
of output power, relative to rising edge of TX_ON (Note 11)
3
µs
Standby-to-Receive Mode
Standby to RX, output settles to within ±2dB of final value
of output power, relative to rising edge of RX_ON (Note 11)
5
µs
AC ELECTRICAL CHARACTERISTICS—SERIAL INTERFACE TIMING
(MAX2820/MAX2821 EV kit: V_CC = +2.7V to +3.6V, registers set to default power-up settings, T_A = +25°C, unless otherwise noted.) (Note 11)
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
SERIAL INTERFACE TIMING (See Figure 1)
t_CSO
t_CSS
t_DS
t_DH
t_CH
t_CL
t_CSH
t_CSW
t_CS1
f_CLK
SCLK rising edge to CSB falling edge wait time
5
Falling edge of CSB to rising edge of first SCLK time
5
Data-to-serial clock setup time
5
Data-to-clock hold time
10
Serial clock pulse-width high
10
Clock pulse-width low
10
Last SCLK rising edge to rising edge of CSB
5
CSB high pulse width
10
Time between the rising edge of CSB and the next rising edge of SCLK
5
Clock frequency
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
MHz
Note 1: Parameters are production tested at +25°C only. Min/max limits over temperature are guaranteed by design and characterization.
Note 2: Defined as the baseband differential RMS output voltage divided by the RMS input voltage (at the RF balun input).
Note 3: Noise-figure specification excludes the loss of the external balun. The external balun loss is typically ~0.5dB.
Note 4: CCK interferer at 25MHz offset. Desired signal equals -73dBm. Interferer amplitude increases until baseband output from
interferer is 10dB below desired signal. Adjacent channel rejection = P_interferer - P_desired.
Note 5: Measured at balun input. Two CW tones at -43dBm with 15MHz and 25MHz spacing from the MAX2820/MAX2821 channel
frequency. IP3 is computed from 5MHz IMD3 product measured at the RX I/Q output.
Note 6: Two CW interferers at -38dBm with 24.5MHz and 25.5MHz spacing from the MAX2820/MAX2821 channel frequency. IP2 is
computed from the 1MHz IMD2 product measured at the RX I/Q output.
Note 7: Output power measured after the matching and balun. TX gain is set to maximum.
Note 8: Adjacent and alternate channel power relative to the desired signal. TX gain is adjusted until the output power is -1dBm.
Power measured with 100kHz video BW and 100kHz resolution BW.
Note 9: Time required to reprogram the PLL, change the operating channel, and wait for the operating channel center frequency to
settle within ±10kHz of the nominal (final) channel frequency.
Note 10: Relative amplitude of reference spurious products appearing in the TX RF output spectrum relative to a CW tone at
0.5MHz offset from the LO.
Note 11: Min/max limits are guaranteed by design and characterization.
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