MAX16008 Datasheet, PDF (7/14 Pages) Maxim Integrated Products – Low-Voltage, High-Accuracy, Quad Window Voltage Detectors in Thin QFN

Low-Voltage, High-Accuracy, Quad Window
Voltage Detectors in Thin QFN
PIN
NAME
Pin Description (continued)
FUNCTION
13 16
14 17
15 18
16 20
17 21
18 22
19 23
—5
— 12
— 13
— 19
EP EP
UVOUT2
OVOUT1
UVOUT1
UVIN1
OVIN1
UVIN2
OVIN2
N.C.
MR
SRT
RESET
EP
Active-Low Undervoltage Output 2. When the voltage at UVIN2 falls below its threshold, UVOUT2
asserts low and stays asserted until the voltage at UVIN2 exceeds its threshold. The open-drain
output has a 30µA internal pullup to V_CC.
Active-Low Overvoltage Output 1. When the voltage at OVIN1 rises above its threshold, OVOUT1
asserts low and stays asserted until the voltage at OVIN1 falls below its threshold. The open-drain
output has a 30µA internal pullup to V_CC.
Active-Low Undervoltage Output 1. When the voltage at UVIN1 falls below its threshold, UVOUT1
asserts low and stays asserted until the voltage at UVIN1 exceeds its threshold. The open-drain
output has a 30µA internal pullup to V_CC.
Undervoltage Threshold Input 1. When the voltage on UVIN1 falls below its threshold, UVOUT1
asserts low.
Overvoltage Threshold Input 1. When the voltage on OVIN1 rises above its threshold, OVOUT1
asserts low.
Undervoltage Threshold Input 2. When the voltages on UVIN2 falls below its threshold, UVOUT2
asserts low.
Overvoltage Threshold Input 2. When the voltage on OVIN2 rises above its threshold, OVOUT2
asserts low.
Not Internally Connected
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to V_CC through a 20kΩ resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The
reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 10⁶ (Ω) x C_SRT (F). Do
not set the reset timeout period to more than 1.12s. For the internal timeout period of 140ms (min),
connect SRT to V_CC.
Active-Low Reset Output. RESET asserts low when the voltage on any of the UVIN_ inputs falls below
their respective thresholds, the voltage on any of the OVIN_ inputs goes above its respective
threshold, or MR is asserted. RESET remains asserted for at least the minimum reset timeout after all
monitored UVIN_ inputs exceed their respective thresholds, all OVIN_ inputs fall below their
respective thresholds, and MR is deasserted. This open-drain output has a 30µA internal pullup.
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low
thermal resistance path from the IC junction to the PC board. Do not use as the only electrical
connection to GND.
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