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MAX1402_07 Datasheet, PDF (7/38 Pages) Maxim Integrated Products – +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC
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+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Note 12: The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen-
tial or pseudo-differential pair. Table 5 shows which inputs form differential pairs.
Note 13: VREF = VREFIN+ - VREFIN-.
Note 14: These specifications apply to CLKOUT only when driving a single CMOS load.
Note 15: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate cor-
rectly.
Note 16: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 17: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 18: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
TIMING CHARACTERISTICS
(V+ = +5V ±5%, VDD = +2.7V to +5.25V, AGND = DGND, fCLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA = TMIN to TMAX,
unless otherwise noted.) (Notes 19, 20, 21)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Master Clock Frequency
Crystal oscillator or clock exter- X2CLK = 0 0.4
fCLKIN nally supplied for specified perfor-
mance (Notes 22, 23)
X2CLK = 1 0.8
2.5
MHz
5.0
Master Clock Input Low Time fCLKIN LO tCLKIN = 1 / fCLKIN, X2CLK = 0
0.4 ·
tCLKIN
ns
Master Clock Input High Time fCLKIN HI tCLKIN = 1 / fCLKIN, X2CLK = 0
0.4 ·
tCLKIN
ns
INT High Time
X2CLK = 0, N = 2(2 · MF1 + MF0)
tINT
280 / N
· tCLKIN
ns
X2CLK = 1, N = 2(2 · MF1 + MF0)
560 / N
· tCLKIN
RESET Pulse Width Low
t2
100
ns
SERIAL-INTERFACE READ OPERATION
INT to CS Setup Time (Note 8)
t3
0
ns
SCLK Setup to Falling Edge CS
t4
30
ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t5
30
ns
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)
t6
SCLK High Pulse Width
t7
SCLK Low Pulse Width
t8
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 21)
t9
VDD = 5V
VDD = 3.3V
0
80
ns
0
100
100
ns
100
ns
0
ns
Bus Relinquish Time After SCLK
Rising Edge (Note 26)
t10
SCLK Rising Edge to INT High
(Note 27)
t11
SERIAL-INTERFACE WRITE OPERATION
SCLK Setup to Falling Edge CS
t12
VDD = 5V
VDD = 3.3V
VDD = 5V
VDD = 3.3V
10
70
ns
10
100
100
ns
200
30
ns
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