MAX1040 Datasheet, PDF (7/44 Pages) Maxim Integrated Products – 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = DV_DD = 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V_REF = 2.5V (MAX1041/MAX1043/
MAX1047/MAX1049), AV_DD = DV_DD = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V_REF = 4.096V
(MAX1040/MAX1042/MAX1046/MAX1048), f_SCLK = 4.8MHz (50% duty cycle), T_A = -40°C to +85°C, unless otherwise noted. Typical
values are at AV_DD = DV_DD = 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV_DD = DV_DD = 5V (MAX1040/MAX1042/
MAX1046/MAX1048), T_A = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC Positive-Supply Rejection
PSRD
AV_DD = 2.7V to 3.6V (MAX1041/
Output _{MAX1043/MAX1047/MAX1049)}
code =
FFFhex ^{AVDD = 4.75V to 5.25V (MAX1040/}
MAX1042/MAX1046/MAX1048)
±0.1
±0.5
mV
±0.1
±0.5
ADC Positive-Supply Rejection
PSRA
Full-
scale
input
AV_DD = 2.7V to 3.6V (MAX1041/
MAX1043/MAX1047/MAX1049)
AV_DD = 4.75V to 5.25V (MAX1040/
MAX1042/MAX1046/MAX1048)
±0.06 ±0.5
mV
±0.06 ±0.5
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
t_CP
40
SCLK Pulse-Width High
t_CH 40/60 duty cycle
16
SCLK Pulse-Width Low
t_CL 60/40 duty cycle
16
GPIO Output Rise/Fall After
CS Rise
t_GOD C_LOAD = 20pF
GPIO Input Setup Before CS Fall t_GSU
0
LDAC Pulse Width
t_LDACPWL
20
SCLK Fall to DOUT Transition
(Note 16)
t_DOT
C_LOAD = 20pF, SLOW = 0
C_LOAD = 20pF, SLOW = 1
1.8
10
SCLK Rise to DOUT Transition
(Notes 16, 17)
t_DOT
C_LOAD = 20pF, SLOW = 0
C_LOAD = 20pF, SLOW = 1
1.8
10
CS Fall to SCLK Fall Setup Time
t_CSS
10
SCLK Fall to CS Rise Setup Time
t_CSH
0
DIN to SCLK Fall Setup Time
t_DS
10
DIN to SCLK Fall Hold Time
t_DH
0
CS Pulse-Width High
t_CSPWH
50
CS Rise to DOUT Disable
t_DOD C_LOAD = 20pF
CS Fall to DOUT Enable
t_DOE C_LOAD = 20pF
1.5
EOC Fall to CS Fall
t_RDS
30
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
ns
ns
ns
100
ns
ns
ns
12.0
ns
40
12.0
ns
40
ns
ns
ns
ns
ns
25
ns
25.0
ns
ns
55
CS or CNVST Rise to EOC Fall
t_DOV
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
CKSEL = 01 (voltage conversion)
120
8
µs
CKSEL = 10 (voltage conversion),
8
internal reference on
CKSEL = 10 (voltage conversion),
80
internal reference initially off
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