DS1340U Datasheet, PDF (7/16 Pages) Maxim Integrated Products – I2C RTC with Trickle Charger

DS1340
I²C RTC with Trickle Charger
when V_CC drops below V_BACKUP. The registers are
maintained from the V_BACKUP source until V_CC is
returned to nominal levels (Table 1). After V_CC returns
above V_PF, read and write access is allowed t_REC.
Oscillator Circuit
The DS1340 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 2 specifies several crys-
tal parameters for the external crystal. Figure 3 shows a
functional schematic of the oscillator circuit. If using a
crystal with the specified characteristics, the startup
time is usually less than one second.
Clock Accuracy
The initial clock accuracy depends on the accuracy of
the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capaci-
tive load for which the crystal was trimmed. Additional
error is added by crystal frequency drift caused by
temperature shifts. External circuit noise coupled into
the oscillator circuit can result in the clock running fast.
Figure 4 shows a typical PC board layout for isolating
Table 2. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal
Frequency
f_O
Series Resistance
ESR
Load Capacitance
C_L
32.768
kHz
80
kΩ
12.5
pF
*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocks for addi-
tional specifications.
RTC
COUNTDOWN
CHAIN
the crystal and oscillator from noise. Refer to
Application Note 58: Crystal Considerations with Dallas
Real-Time Clocks (www.maximintegrated.com/RTCapps)
for detailed information.
DS1340C Only
The DS1340C integrates a standard 32,768Hz crystal
into the package. Typical accuracy with nominal V_CC
and +25°C is approximately +15ppm. Refer to
Application Note 58 for information about crystal accu-
racy vs. temperature.
Operation
The DS1340 operates as a slave device on the serial
bus. Access is obtained by implementing a START
condition and providing a device identification code fol-
lowed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The
device is fully accessible and data can be written and
read when V_CC is greater than V_PF. However, when
V_CC falls below V_PF, the internal clock registers are
blocked from any access. If V_PF is less than V_BACKUP,
the device power is switched from V_CC to V_BACKUP
when V_CC drops below V_PF. If V_PF is greater than
V_BACKUP, the device power is switched from V_CC to
V_BACKUP when V_CC drops below V_BACKUP. The regis-
ters are maintained from the V_BACKUP source until V_CC
is returned to nominal levels. The functional diagram
(Figure 5) shows the main elements of the serial RTC.
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
C_L1
C_L2
RTC
REGISTERS
GND
X1
X2
CRYSTAL
Figure 3. Oscillator Circuit Showing Internal Bias Network
Figure 4. Layout Example
Maxim Integrated
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