DG421CJ Datasheet, PDF (7/12 Pages) Maxim Integrated Products – Improved Low-Power, CMOS Analog Switches with Latches

Improved Low-Power,
CMOS Analog Switches with Latches
_________________________________Timing Diagrams/Test Circuits (continued)
3V
LOGIC
INPUT 0V
SWITCH
OUTPUT 1 ^0V
50%
VOUT1
0.9 x VOUT
VOUT2
0.9 x VOUT
SWITCH
OUTPUT 2 _0V
tD
tD
Figure 4. DG423 Break-Before-Make Interval
VOUT
IN 0FF
0N
+5V
+15V
V_D = 10V
VD = 10V
LOGIC
INPUT
D ^{VL RS}
D
IN
WR
GND
V+
S
S
RL2
300Ω
V-
-15V
C_L INCLUDES FIXTURE AND STRAY CAPACITANCE.
DG423
VOUT2
RL1
C_L2 ^300Ω
35pF
R_L = 1000Ω
CL = 35pF
VOUT1
C_L1
35pF
∆VOUT
0FF
+5V
RS VL
Rg
S
+15V
V+
D
V_g
GND WR IN V-
DG421
DG423
DG425
V_OUT
CL
10nF
Q = ∆VOUT x CL
IN DEPENDENT ON SWITCH CONFIGURATION.
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 5. Charge Injection
-15V
VIN = 3V
10nF
+15V
SIGNAL GENERATOR
VS
D ^V+
+5V
RS VL
IN
NETWORK
ANALYZER
VD
R_L
S
GND WR
V-
-15V 10nF
0V or 2.4V
DG421
DG423
DG425
Figure 6 . Off-Isolation Rejection Ratio
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