MAX4613_07 Datasheet, PDF (6/10 Pages) Maxim Integrated Products – Quad, SPST Analog Switch

Quad, SPST Analog Switch
PIN
DIP/SO/TSSOP
1, 8, 9, 16
2, 7, 10, 15
3, 6, 11, 14
4
5
12
13
—
THIN QFN
6, 7, 14, 15
5, 8, 13, 16
1, 4, 9, 12
2
3
10
11
EP
Pin Description
NAME
IN1–IN4
D1–D4
S1–S4
V-
GND
VL
V+
PAD
FUNCTION
Logic Control Input
Analog-Switch Drain Output
Analog-Switch Source Output
Negative-Supply Voltage Input
Ground
Logic-Supply Voltage Input
Positive-Supply Voltage Input—Connected to Substrate
Exposed Pad. Connect PAD to V+.
Applications Information
General Operation
1) Switches are open when power is off.
2) IN_, D_, and S_ should not exceed V+ or V-, even
with the power off.
3) Switch leakage is from each analog switch terminal
to V+ or V-, not to other switch terminals.
Operation with Supply Voltages
Other than ±15V
Using supply voltages less than ±15V will reduce the
analog signal range. The MAX4613 operates with
±4.5V to ±20V bipolar supplies or with a +4.5V to +40V
single supply; connect V- to GND when operating with
a single supply. Also, all device types can operate with
unbalanced supplies such as +24V and -5V. V_L must
be connected to +5V to be TTL compatible, or to V+ for
CMOS-logic level inputs. The Typical Operating
Characteristics graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
V_L, V-, and logic inputs. If power-supply sequencing
is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
V+
S
D
V_g
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
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