MAX3890 Datasheet, PDF (6/12 Pages) Maxim Integrated Products – +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________Detailed Description
The MAX3890 converts 16-bit-wide, 155Mbps data to
2.5Gbps serial data (Figure 1). It is composed of a 16-
bit parallel input register, a 16-bit shift register, control
and timing logic, PECL output buffers, LVDS input/out-
put buffers, and a frequency-synthesizing PLL (consist-
ing of a phase/frequency detector, loop filter/amplifier,
voltage-controlled oscillator (VCO), and prescaler).
The PLL synthesizes an internal 2.5Gbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
The incoming parallel data is clocked into the
MAX3890 on the rising transition of the parallel-clock-
input signal (PCLKI). Proper operation is ensured if the
parallel input register is latched within a window of time
(t_SKEW) that is defined with respect to the parallel-
clock-output signal (PCLKO). PCLKO is the synthe-
sized 2.5Gbps internal serial-clock signal divided by
16. The allowable PCLKO-to-PCLKI skew is 0 to +4ns.
This defines a timing window after the PCLKO rising
edge, during which a PCLKI rising edge may occur
(Figure 2).
System Loopback
The MAX3890 is designed to allow system loopback test-
ing. The loopback outputs (SLBO+, SLBO-) of the
MAX3890 may be directly connected to the loopback
inputs of a deserializer (such as the MAX3880) for system
diagnostics. To enable the SLBO outputs, apply a TTL
logic-high signal to the SOS input. Note: The same signal
that controls the SOS enable input may also be used to
control the SIS enable input on the MAX3880.
PDI15+
PDI15-
LVDS
PDI1+
PDI1-
LVDS
16-BIT
PARALLEL
INPUT
REGISTER
MAX3890
PDI0+
PDI0-
PCLKI+
PCLKI-
RCLKI+
RCLKI-
LVDS
LVDS
PRESCALER
LVDS
PHASE/FREQ
FILTER
VCO
DETECT
PLL
DIVIDE
BY 16
LVDS
SHIFT
LATCH
16-BIT
SHIFT
REGISTER
SOS
SLBO+
CML
SLBO-
SDO+
PECL
SDO-
SCLKO+
PECL
SCLKO-
Figure 1. Functional Diagram
FIL+ FIL-CLKSET
PCLKO+ PCLKO-
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