MAX3518ETPT Datasheet, PDF (6/9 Pages) Maxim Integrated Products – DOCSIS 3.0 Upstream Amplifier

DOCSIS 3.0 Upstream Amplifier
PIN
1, 5
2
3
4, 11
6
7
8
9
10
12
13, 15, 16, 18,
19, 20
14
17
—
NAME
GND
IN+
IN-
N.C.
SCLK
SDA
CS
TXEN
VCC
OUT-
N.C.
OUT+
VCC
EP
 Pin Description
FUNCTION
Ground
Positive PGA Input
Negative PGA Input
No Connection. These pins must remain open.
Serial Interface Clock
Serial Interface Data
Serial Interface Enable
Transmit Enable. TXEN = high places the device in transmit mode.
Supply Voltage for Serial Interface
Negative Output
No Connection. Connect these pins to ground.
Positive Output
Supply Voltage for Programmable-Gain Amplifier (PGA)
Ground
Table 1. Register Description
REGISTER
REGISTER
DATA 8 BITS
NAME
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
Power/Gain
0000
PC2
PC1
GC5
GC4
GC3
GC2
GC1
GC0
Initialize
0001
0
0
0
0
0
0
0
0
 Detailed Description
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA) provides 63dB
of output level control in 1dB steps. The gain of the
PGA is determined by a 6-bit gain code (GC5–GC0)
programmed through the serial data interface (Tables
1 and 2). Specified performance is achieved when the
input is driven differentially.
Four power codes (PC1–PC0) allow the PGA to be used
with reduced bias current when distortion performance
can be relaxed. In addition, for each power code, bias
current is automatically reduced with gain code for
maximum efficiency.
The PGA features a differential Class A output stage
capable of driving four +58dBmV QPSK modulated
signals, or a single +64dBmV QPSK modulated signal
into a 75Ω load. This architecture provides superior
even-order distortion performance but requires that a
transformer be used to convert to a single-ended out-
put. In transmit-disable mode, the output amplifiers
are powered down, resulting in low output noise, while
maintaining impedance match.
3-Wire Serial Interface (SPI)
and Control Registers
The MAX3518 includes two programmable registers
for initializing the part and setting the gain and power
consumption. The 4 MSBs are address bits; the 8 least
significant bits (LSBs) are used for register data. Data is
shifted MSB first.
Note: The registers must be written 100µs after the
device is powered up, and no earlier. Once a new set
of register data is clocked in, the corresponding power
code and/or gain code does not take effect until TXEN
transitions from high to low.
 Applications Information
Power Codes
The MAX3518 is designed to meet the stringent linearity
requirements of DOCSIS 3.0 using power code (PC) 3.
For DOCSIS 2.0, PC = 1 is recommended, which results
in substantial supply current reduction. The full range of
gain codes can be used in any power code. The gain
difference between power codes is typically less than
0.1dB.
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