MAX16824_08 Datasheet, PDF (6/15 Pages) Maxim Integrated Products – High-Voltage, Three-Channel Linear High-Brightness LED Drivers

High-Voltage, Three-Channel Linear
High-Brightness LED Drivers
PIN
MAX16824 MAX16825
1
1
2
3
4
5, 6, 10, 14
7
2
3
4
5, 14
—
8
—
9
—
11
11
12
12
13
13
15
15
16
16
—
7
—
8
—
9
—
10
—
6
—
—
Pin Description
NAME
FUNCTION
OUT1
CS1
IN
REG
N.C.
PWM1
PWM2
PWM3
GND
OUT3
CS3
CS2
OUT2
DIN
LE
OE
DOUT
CLK
EP
Channel 1 LED Driver Output. OUT1 is an open-drain, constant-current-sinking output
rated to 36V.
Channel 1 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS1 and GND to program the output current level for channel 1.
Positive Input Supply. Bypass with a 0.1µF (min) capacitor to GND.
+5V-Regulated Output. Connect a 1µF capacitor from REG to GND.
No Connection. Must be left unconnected.
Dimming Input 1. PWM1 is a dimming input for channel 1. A logic-low turns off OUT1 and
a logic-high turns on OUT1.
Dimming Input 2. PWM2 is a dimming input for channel 2. A logic-low turns off OUT2 and
a logic-high turns on OUT2.
Dimming Input 3. PWM3 is a dimming input for channel 3. A logic-low turns off OUT3 and
a logic-high turns on OUT3.
Ground
Channel 3 LED Driver Output. OUT3 is an open-drain, constant-current-sinking output
rated to 36V.
Channel 3 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS3 and GND to program the output current level for channel 3.
Channel 2 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS2 and GND to program the output current level for channel 2.
Channel 2 LED Driver Output. OUT2 is an open-drain, constant-current-sinking output
rated to 36V.
Serial-Data Input. Data is loaded into the internal 3-bit shift register on the rising edge of
CLK.
Latch-Enable Input. Data loaded transparently from the internal shift register to the
output latch while LE is high. Data is latched into the output latch on the LE’s falling edge
and retained while LE is low.
Output Enable Input. Drive OE high to place all outputs into a high-impedance mode
without altering the contents of the output latches. Drive OE low to force all outputs to
follow the state of the output latches.
Serial-Data Output. Data is clocked out of the internal 3-bit shift register to DOUT on the
rising edge of CLK. DOUT is a replica of the shift register’s last bit.
Clock Input
Exposed Paddle. Connect EP to a large-area ground plane for effective power
dissipation. Do not use as the IC ground connection.
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