MAX1638 Datasheet, PDF(6/16 Page) Maxim Integrated Products – High-Speed Step-Down Controller with Synchronous Rectification for CPU Power

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MAX1638 Datasheet, PDF (6/16 Pages) Maxim Integrated Products – High-Speed Step-Down Controller with Synchronous Rectification for CPU Power

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High-Speed Step-Down Controller with

Synchronous Rectification for CPU Power

______________________________________________________________Pin Description

5, 6, 7

16, 17

NAME

BST

PWROK

CSL

CSH

FUNCTION

Boost-Capacitor Bypass for High-Side MOSFET Gate Drive. Connect a 0.1ÂµF capacitor and low-leak-

age Schottky diode as a bootstrapped charge-pump circuit to derive a 5V gate drive from VDD for DH.

Open-Drain Logic Output. PWROK is high when the voltage on FB is within +8% and -6% of its set-

point.

Current-Sense Amplifierâs Inverting Input. Place the current-sense resistor very close to the controller IC,

and use a Kelvin connection.

Current-Sense Amplifierâs Noninverting Input

D2, D1, Digital Inputs for Programming the Output Voltage. D0âD4 are logic inputs that set the output to a volt-

age between 1.3V and 3.5V (Table 2). D0âD4 are internally pulled up to VCC with 5ÂµA current sources.

VCC

REF

AGND

CC1

CC2

FREQ

D4, D3

NDRV

PDRV

VDD

PGND

Loop Gain-Control Input. LG is a three-level input that is used to trade off loop gain vs. AC load-regula-

tion and load-transient response. Connect LG to VCC, REF, or AGND for 2%, 1%, or 0.5% AC load-reg-

ulation errors, respectively.

Analog Supply Input, 5V. Use an RC filter network, as shown in Figure 1.

Reference Output, 3.5V. Bypass REF to AGND with 0.1ÂµF (min). Sources up to 100ÂµA for external

loads. Force REF below 2V to turn off the controller.

Analog Ground

Voltage-Feedback Input. Connect FB to the CPUâs remote voltage-sense point. The voltage at this input

is regulated to a value determined by D0âD4.

Fast-Loop Compensation Capacitor Input. Connect a ceramic capacitor and resistor in series from

CC1 to AGND. See the section Compensating the Feedback Loop.

Slow-Loop Compensation Capacitor Input. Connect a ceramic capacitor from CC2 to AGND. See the

section Compensating the Feedback Loop.

Frequency-Select Input. FREQ = VCC: 1MHz

FREQ = REF: 600kHz

FREQ = AGND: 300kHz

Digital Inputs for Programming the Output Voltage

GlitchCatcher N-Channel MOSFET Driver Output. NDRV swings between VDD and PGND.

GlitchCatcher P-Channel MOSFET Driver Output. PDRV swings between VDD and PGND.

5V Power Input for MOSFET Drivers. Bypass VDD to PGND within 0.2 in. (5mm) of the VDD pin using a

0.1ÂµF capacitor and 4.7ÂµF capacitor connected in parallel.

Low-Side Synchronous Rectifier Gate-Drive Output. DL swings between PGND and VDD. See the

section BST High-Side Gate-Driver Supply and MOSFET Drivers.

Power Ground

Switching Node. Connect LX to the high-side MOSFET source and inductor.

High-Side Main MOSFET Switch Gate-Drive Output. DH is a floating driver output that swings from LX

to BST, riding on the LX switching-node voltage. See the section BST High-Side Gate-Driver Supply

and MOSFET Drivers.

6 _______________________________________________________________________________________

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