MAX16046_09 Datasheet, PDF (6/70 Pages) Maxim Integrated Products – 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers

12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(V_CC = 3V to 14V, T_A = -40°C to +85°C, unless otherwise specified. Typical values are at V_CC = 3.3V, T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input Leakage Current
V_CC shorted to GND, SCL/SDA at 0V or
-1
3.3V
-1
+1
µA
+1
Output-Voltage Low
Input Capacitance
SMBUS TIMING
Serial Clock Frequency
Bus Free Time Between STOP
and START Condition
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
Clock High Period
Data Setup Time
Output Fall Time
Data Hold Time
Pulse Width of Spike Suppressed
JTAG INTERFACE
V_OL
I_SINK = 3mA
C_IN
f_SCL
t_BUF
t_SU:STA
t_HD:STA
t_SU:STO
t_LOW
t_HIGH
t_SU:DAT
t_OF
t_HD:DAT
t_SP
10pF ≤ C_BUS ≤ 400pF
From 50% SCL falling to SDA change
0.4
V
5
pF
400
kHz
1.3
µs
0.6
µs
0.6
µs
0.6
µs
1.3
µs
0.6
µs
100
ns
250
ns
0.3
0.9
µs
30
ns
TDI, TMS, TCK Logic-Low Input
Voltage
V_IL
Input voltage falling
0.55
V
TDI, TMS, TCK Logic-High Input
Voltage
V_IH
Input voltage rising
2
V
TDO Logic-Output Low Voltage
V_{OL_TDO} V_DBP ≥ 2.5V, I_SINK = 2mA
TDO Logic-Output High Voltage
V_{OH_TDO} V_DBP ≥ 2.5V, I_SOURCE = 200mA
2.4
TDO Leakage Current
TDO high impedance
-1
0.4
V
V
+1
µA
TDI, TMS Pullup Resistors
R_JPU
Pullup to V_DBP
7
10
13
kΩ
Input/Output Capacitance
C_I/O
JTAG TIMING
5
pF
TCK Clock Period
t₁
1000
ns
TCK High/Low Time
t_2, t₃
50
500
ns
TCK to TMS, TDI Setup Time
t₄
TCK to TMS, TDI Hold Time
t₅
TCK to TDO Delay
t₆
15
ns
15
ns
500
ns
TCK to TDO High-Impedance
Delay
t₇
500
ns
EEPROM TIMING
EEPROM Byte Write Cycle Time
t_WR
(Note 6)
10.5
12
ms
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at T_A = +25°C
and T_A = +85°C. Specifications at T_A = -40°C are guaranteed by design.
Note 2: V_UVLO is the minimum voltage on V_CC to ensure the device is EEPROM configured.
Note 3: Applies to RESET, fault, delay, and watchdog timeouts.
Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
Note 5: Guaranteed by design.
Note 6: An additional cycle is required when writing to configuration memory for the first time.
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