MAX1403_02 Datasheet, PDF(6/36 Page) Maxim Integrated Products – +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC

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MAX1403_02 Datasheet, PDF (6/36 Pages) Maxim Integrated Products – +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC

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+3V, 18-Bit, Low-Power, Multichannel,

Oversampling (Sigma-Delta) ADC

ELECTRICAL CHARACTERISTICS (continued)

(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless

otherwise noted. Typical values are at TA = +25Â°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

POWER DISSIPATION (V+ = VDD = +3.3V, digital inputs = 0 or VDD, external CLKIN, burn-out and transducer excitation currents

disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)

Power Dissipation

Standby Power Dissipation

Normal mode,

MF1 = 0,

MF0 = 0

Buffers off

1.024MHz

Buffers on

Buffers off

2.4576MHz

Buffers on

2X mode,

MF1 = 0,

MF0 = 1

4X mode,

MF1 = 1,

MF0 = 0

Buffers off

1.024MHz

Buffers on

Buffers off

2.4576MHz

Buffers on

Buffers off

1.024MHz

Buffers on

Buffers off

2.4576MHz

Buffers on

8X mode,

MF1 = 1,

MF0 = 1

Buffers off

1.024MHz

Buffers on

Buffers off

2.4576MHz

Buffers on

(Note 19)

0.81 1.36

1.45 2.05

1.32 1.98

2.51 3.30

1.08

2.28

1.95 2.97

4.53 6.11

1.75

4.32

6.67 8.58

16.6 21.2

6.44

16.4

7.0

8.91

16.9 21.45

ÂµW

Note 1: Contact factory for INL limits applicable with FS1 = 0 and MF1, MF0 = 1, 2, or 3.

Note 2: Nominal gain is 0.98. This ensures a full-scale input voltage may be applied to the part under all conditions without caus-

ing saturation of the digital output data.

Note 3: Positive Full-Scale Error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar

and bipolar input ranges. This error does not include the nominal gain of 0.98.

Note 4: Full-Scale Drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar

input ranges.

Note 5: Gain Error does not include zero-scale errors. It is calculated as (full-scale error - unipolar offset error) for unipolar ranges

and as (full-scale error - bipolar zero error) for bipolar ranges. This error does not include the nominal gain of 0.98.

Note 6: Gain-Error Drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if zero-scale

error is removed.

Note 7: Use of the offset DAC does not imply that any input may be taken below AGND.

Note 8: Additional noise added by the offset DAC is dependent on the filter cutoff, gain, and DAC setting. No noise is added for a

DAC code of 0000.

Note 9: Guaranteed by design or characterization; not production tested.

Note 10: The absolute input voltage must be within the input voltage range specification.

Note 11: All AIN and REFIN pins have identical input structures. Leakage is production tested only for the AIN3, AIN4, AIN5,

CALGAIN, and CALOFF inputs.

Note 12: The dynamic load presented by the MAX1403 analog inputs for each gain setting is discussed in detail in the Switching

Network section. Values are provided for the maximum allowable external series resistance.

Note 13: The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen-

tial or pseudo-differential pair. Table 5 shows which inputs form differential pairs.

Note 14: VREF = VREFIN+ - VREFIN-.

Note 15: These specifications apply to CLKOUT only when driving a single CMOS load.

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