DS8024_V3 Datasheet, PDF (6/15 Pages) Maxim Integrated Products – Smart Card Interface

Smart Card Interface
PIN
1, 2
3
4
5, 7
6
8
9
10
11
12, 13
14
15
16
17
18
19
20
21
22
23
24, 25
26
27, 28
Pin Description
NAME
CLKDIV1,
CLKDIV2
5V/3V
PGND
CP2, CP1
V_DDA
V_UP
PRES
PRES
I/O
AUX2,
AUX1
CGND
CLK
RST
V_CC
N.C.
CMDVCC
RSTIN
V_DD
GND
OFF
XTAL1,
XTAL2
I/OIN
AUX1IN,
AUX2IN
FUNCTION
Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects
5V operation; logic-low selects 3V operation. See Table 3 for a complete description of choosing card
voltages.
Analog Ground
Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100m
)
between CP1 and CP2.
Charge-Pump Supply. Must be equal to or higher than V_DD. Connect a supply of at least 3.3V.
Charge-Pump Output. Connect a 100nF capacitor (ESR < 100m
) between V_UP and GND.
Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
Smart Card Data-Line Output. Card data communication line, contact C7.
Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1) and
C8 (AUX2).
Smart Card Ground
Smart Card Clock. Card clock, contact C3.
Smart Card Reset. Card reset output from contact C2.
Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100m
).
No Connection. Unused on the DS8024.
Activation Sequence Initiate. Active-low input from host.
Card Reset Input. Reset input from the host.
Supply Voltage
Digital Ground
Status Output. Active-low interrupt output to the host. Use a 20k
integrated pullup resistor to V_DD.
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on XTAL1.
I/O Input. Host-to-interface chip data I/O line.
C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.
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