DS4625 Datasheet, PDF (6/6 Pages) Maxim Integrated Products – 3.3V Dual-Output LVPECL Clock Oscillator

3.3V Dual-Output LVPECL Clock Oscillator
Pin Configuration
TOP VIEW
N.C.
+ _A1
OE 1
N.C.
A2
6 V_CC
GND 2
DS4625
5 ON1
GND 3 *EP
A3
4 OP1
A4
OP2
ON2
(5.00mm × 3.20mm × 1.49mm)
*EXPOSED PAD
Detailed Description
The DS4625 is a dual-output, low-jitter clock oscillator
that produces frequency output pair combinations as
shown in the Ordering Information/Selector Guide table.
The phase relationship between the outputs is not guar-
anteed. The device combines an AT-cut, fundamental-
mode crystal, an oscillator, and a low-noise PLL in a
5.0mm x 3.2mm surface-mount LCCC package.
The DS4625 provides dual LVPECL clock output dri-
vers. The output drivers can be enabled and disabled
through the OE pin. The OE pin is an active-high CMOS
input that has an internal pullup resistor. When OE is
high, both output pairs are enabled.
Chip Information
PROCESS: Bipolar SiGe
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 LCCC
L1053+H2
21-0389
Typical Application Circuit
0.1μF
0.01μF
V_CC
OP1
DS4625
ON1
OE
OP2
GND
ON2
50Ω
PECL_BIAS AT V_CC - 2.0V
50Ω
50Ω
PECL_BIAS AT V_CC - 2.0V
50Ω
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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