DS2465 Datasheet, PDF (6/31 Pages) Maxim Integrated Products – SHA-256 Coprocessor with 1-Wire Master Function

ABRIDGED DATA SHEET
DS2465
SHA-256 Coprocessor with 1-Wire Master Function
1-Wire PORT
VCC
CONFIGURATION
AND TIMING
REGISTERS
T-TIME OSCILLATOR
SDA
I²C
INTERFACE
SCL
CONTROLLER
IO
CONTROLLER
LINE
TRANSCEIVER
IO
SLPZ
1-Wire MASTER
STATUS REGISTER
GND
1-WIRE READ
DATA REGISTER
SCRATCHPAD
DS2465
Refer to the full data sheet for this
information.
USER EEPROM
PAGES
Refer to the full
data sheet.
Figure 1. Block Diagram
Memory
Figure 2 shows the memory organization of the DS2465.
The memory begins at address 00h with the input
scratchpad. The register section follows at address 60h.
Addresses 00 to 6F
are implemented as
volatile SRAM. The 1-Wire port configuration settings
have default values that are loaded automatically during
power-on. The address range 70h and higher is non-
volatile. It contains factory-programmed device identi-
fication data, a personality byte, and the user memory
pages.
Refer to the full data sheet for this information.
����������������������������������������������������������������� Maxim Integrated Products  6