DG444DY-T Datasheet, PDF (6/10 Pages) Maxim Integrated Products – Improved, Quad, SPST Analog Switches

Improved, Quad, SPST Analog Switches
_____________________Pin Description
PIN
DIP/SO THIN QFN
1, 16, 9, 8 15, 14, 7, 6
2, 15, 10, 7 16, 13, 8, 5
3, 14, 11, 6 1, 12, 9 4
4
2
5
3
12
10
13
11
—
EP
NAME
IN1–IN4
D1–D4
S1–S4
V-
GND
VL
V+
PAD
FUNCTION
Logic Control
Inputs
Drain Outputs
Source Outputs
Negative-Supply
Voltage Input
Ground
Logic-Supply
Voltage Input
Positive-Supply-
Voltage
Input—Connected
to Substrate
Exposed Pad
Connect Pad to V+
Applications Information
General Operation
• Switches are open when power is off.
• IN, D, and S should not exceed V+ or V-, even with
the power off.
• Switch leakage is from each analog switch terminal
to V+ or V-, not to other switch terminals.
Operation with Supply Voltages
Other than ±15V
Using supply voltages other than ±15V will reduce the
analog signal range. The DG444/DG445 switches oper-
ate with ±4.5V to ±20V bipolar supplies or with a +10V
to +30V single supply; connect V- to 0V when operating
with a single supply. Also, all device types can operate
with unbalanced supplies such as +24V and -5V. V_L
must be connected to +5V to be TTL compatible, or to
V+ for CMOS-logic level inputs. The Typical Operating
Characteristics graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
V_L , V-, and logic inputs. If power-supply sequenc-
ing is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
V+
S
D
V_g
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
LOGIC +3V
INPUT
0V
SWITCH
OUTPUT
0V
tf < 20ns
50%
tr < 20ns
t_OFF
V_OUT
0.8 x V_OUT
0.8 x V_OUT
t_ON
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching Time
SWITCH
INPUT
LOGIC
INPUT
+3V
+5V
V_L
D
IN
GND
+15V
V+
S
V-
DG444
DG445
R_L
V_OUT
C_L
-15V
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
C_L INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) ^VOUT ^{= V}D
R_L
R_L + r_DS(ON)
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