DG411CJ Datasheet, PDF (6/12 Pages) Maxim Integrated Products – Improved, Quad, SPST Analog Switches

Improved, Quad,
SPST Analog Switches
______________________________________________________________Pin Description
PIN
1, 16, 9, 8
2, 15, 10, 7
3, 14, 11, 6
4
5
12
13
NAME
IN1-IN4
D1-D4
S1-S4
V-
GND
V_L
V+
FUNCTION
Inputs
Analog-Switch Drain Terminal
Analog-Switch Source Terminal
Negative Supply-Voltage Input
Ground
Logic Supply Voltage
Positive Supply-Voltage Input—connected to substrate
__________Applications Information
Operation with Supply Voltages
Other Than 15V
Using supply voltages other than 15V will reduce the
analog signal range. The DG411/DG412/DG413 switch-
es operate with ±4.5V to ±20V bipolar supplies or with
a +10V to +30V single supply; connect V- to 0V when
operating with a single supply. Also, all device types
can operate with unbalanced supplies such as +24V
and -5V. V_L must be connected to +5V to be TTL com-
patible, or to V+ for CMOS-logic level inputs. The
Typical Operating Characteristics graphs show typical
on-resistance with ±15V, ±10V, and ±5V supplies.
(Switching times increase by a factor of two or more for
operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings because stresses beyond the listed rat-
ings may cause permanent damage to the devices.
Always sequence V+ on first, followed by V_L, V-, and
logic inputs. If power-supply sequencing is not possi-
ble, add two small, external signal diodes in series with
supply pins for overvoltage protection (Figure 1).
Adding diodes reduces the analog signal range to 1V
below V+ and 1V below V-, without affecting low switch
resistance and low leakage characteristics. Device
operation is unchanged, and the difference between
V+ and V- should not exceed +44V.
V+
D
Vg
V+
S
V-
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
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