MAX3956 Datasheet, PDF (54/82 Pages) Maxim Integrated Products – Transceiver with DDM and DC-Coupled Laser Interface

MAX3956
11.3Gbps Transceiver with DDM and
DC-Coupled Laser Interface
Interrupt Mask Control Register (INTMSK1), Address: H0x5E (Page 0)
BIT
D[7:5]
D4
D3
Bit Name
RES
INTMSK_RXLOSREF
INTMSK_RXLOS
Read/Write
R/W Write in setup mode only
POR State
011
1
1
The INTMSK1 register sets mask bits preventing individual events to latch interrupt at INTRPT pin.
BIT
NAME
DESCRIPTION
D[7:5]
RES
Reserved
D[2:0]
RES
111
Mask RXLOSREF interrupt from INTRPT pin and TOPSTAT register
D[4]
INTMSK_RXLOSREF 0 = no mask
1 = mask (default)
D[3]
D[2:0]
INTMSK_RXLOS
RES
Mask RXLOS copy from INTRPT pin and TOPSTAT register
0 = no mask
1 = mask (default)
Reserved
Interrupt Mask Control Register (INTMSK2), Address: H0x5F (Page 0)
BIT
D7
D6
D5
D4
D3
D2
D1
Bit Name
INTMSK_
LVFLAG
RES
INTMSK_
TIN_LOS
RES
INTMSK_
TOUTA
INTMSK_
TOUTC
INTMSK_
VOUT
Read/Write
R/W Write in setup mode only
POR State
1
1
1
1
1
1
1
The INTMSK2 register sets mask bits preventing individual events to latch interrupt at INTRPT pin.
BIT
NAME
DESCRIPTION
Mask LVFLAG interrupt from INTRPT pin and TOPSTAT register
D[7]
INTMSK_LVFLAG 0 = no mask
1 = mask (default)
D[6]
RES
Reserved
Mask TIN_LOS interrupt from INTRPT pin and TOPSTAT register
D[5]
INTMSK_TIN_LOS 0 = no mask
1 = mask (default)
D[4]
RES
Reserved
Mask LV_TOUTA interrupt from INTRPT pin and TOPSTAT register
D[3]
INTMSK_TOUTA
0 = no mask
1 = mask (default)
Mask LV_TOUTC interrupt from INTRPT pin and TOPSTAT register
D[2]
INTMSK_TOUTC
0 = no mask
1 = mask (default)
Mask LV_VOUT interrupt from INTRPT pin and TOPSTAT register
D[1]
INTMSK_VOUT
0 = no mask
1 = mask (default)
Mask fault event from INTRPT pin
D[0]
INTMSK_FAULT
0 = no mask
1 = mask (default)
D0
INTMSK_
FAULT
1
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