MAX9424 Datasheet, PDF (5/11 Pages) Maxim Integrated Products – Lowest Jitter Quad PECL-to-ECL Differential Translators

PIN
1, 8
2
3
4
5
6
7
9
10
11, 17, 24,
30
12
13
14, 20, 21,
27
15
16
18
19
22
23
25
26
28
29
31
32
Lowest Jitter Quad PECL-to-ECL
Differential Translators
NAME
V_CC
SEL
SEL
CLK
CLK
EN
EN
IN3
IN3
V_GG
OUT3
OUT3
V_EE
IN2
IN2
OUT2
OUT2
OUT1
OUT1
IN1
IN1
OUT0
OUT0
IN0
IN0
Pin Description
FUNCTION
Positive Supply Voltage. Bypass V_CC to V_GG with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverting Differential Select Input. Setting SEL = 1 and SEL = 0 enables all four channels to
operate independently. Setting SEL = 0 and SEL = 1 enables all four channels to be synchronized to
CLK.
Inverting Differential Select Input
Noninverting Differential Clock Input
Inverting Differential Clock Input
Noninverting Differential Output Enable Input. Setting EN = 1 and EN = 0 enables all four outputs.
Setting EN = 0 and EN = 1 disables all four outputs.
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
Ground Reference
Inverting Differential Output 3
Noninverting Differential Output 3
Negative Supply Voltage. Bypass from V_EE to V_GG with 0.1µF and 0.01µF ceramic capacitors. Place
the capacitors as close to the device as possible with the smaller value capacitor closest to the
device.
Noninverting Differential Input 2
Inverting Differential Input 2
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
Noninverting Differential Input 0
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