MAX847 Datasheet, PDF (5/18 Pages) Maxim Integrated Products – 1-Cell, Step-Up Two-Way Pager System IC

1-Cell, Step-Up
Two-Way Pager System IC
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
CH2 Input Hysteresis (Note 15)
1
2
4
mV
CH0 Input Current
CH0 = 0.2V to 1.27V
-100
100
nA
CH Comparator Response Time
(Note 15)
10mV overdrive
0.6
1.0
µs
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
Note 2: This is not a tested parameter, since the IC is powered from OUT, not BATT. The only limitation in the BATT range is the
inability to generate more than 5 times, or less than 1.15 times the BATT voltage at OUT. This is due to PWM controller
duty-cycle limitations in Run Mode.
Note 3: Minimum start-up voltage is tested by determining when the LX pins can draw at least 50mA for 1µs (min) at a 50kHz (min)
repetition rate. This guarantees that the IC will deliver at least 200µA at the OUT pin.
Note 4: This supply current is drawn from the OUT pin. Current drain from the battery depends on voltages at BATT and OUT and
on the DC-to-DC converter’s efficiency.
Note 5: Current into BATT pin in addition to the supply current at OUT. This current is roughly constant from Coast to Run Mode.
Note 6: Current into NICD pin when NICD isn’t being charged and isn’t regulating OUT.
Note 7: Current into NICD pin when NICD is regulating OUT. Doesn’t include current drawn from OUT by the rest of the circuit.
Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V.
Note 8: Current into NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won’t draw significant current
when the main battery is removed and backup is not activated.
Note 9: Serial-interface timing specifications are not tested and are provided for design guidance only. Serial-interface functionali-
ty is tested by clocking data in at 5MHz with a 50% duty-cycle clock and checking for proper operation. With OUT set
below 2.5V, the serial-interface clock frequency should be reduced to 1MHz to ensure proper operation.
Note 10: This specification is not directly tested but is guaranteed by correlation to LX on-resistance and current-limit tests.
Note 11: Measured by using the internal feedback network and Coast-Mode error comparator to regulate OUT. Doesn’t include
ripple voltage due to inductor currents.
Note 12: Measured by using the internal feedback network and Run-Mode error comparator to regulate OUT. Doesn’t include ripple
voltage due to inductor currents.
Note 13: Uses the OUT measurement techniques described for the OUT Error, Coast Mode, and OUT Error Run Mode specifications.
Note 14: PLL acquisition characteristics depend on the impedance at the FILT pin. The specification is not tested and is provided
for design guidance only.
Note 15: The limits in this specification are not guaranteed and are provided for design guidance only.
__________________________________________Typical Operating Characteristics
(Circuit of Figure 2, T_A = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
(RUN MODE, V_OUT = 3.0V)
100
90
EFFICIENCY vs. LOAD CURRENT
(COAST MODE, V_OUT = 3.0V)
100
V_IN = 2.0V
V_IN = 1.5V
90
EFFICIENCY vs. LOAD CURRENT
(COAST MODE, V_OUT = 2.4V)
100
90
V_IN = 2.0V
V_IN = 1.5V
80
80
V_IN = 0.8V
V_IN = 1.2V
80
70
V_IN = 1.0V
70
V_IN = 1.0V
V_IN = 1.2V
V_IN = 0.8V
60
60
V_IN = 2.0V
50
V_IN = 1.5V
50
70
V_IN = 1.0V ^{VIN = 1.2V}
60
V_IN = 0.8V
50
40
1
10
100
LOAD CURRENT (mA)
40
1000
0.1
1
10
100
1000
LOAD CURRENT (mA)
40
0.1
1
10
100
1000
LOAD CURRENT (mA)
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