MAX6391 Datasheet, PDF (5/9 Pages) Maxim Integrated Products – Dual-Voltage uP Supervisory Circuits with Sequenced Reset Outputs

Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
Pin Description
PIN
MAX6391 MAX6392
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
—
—
8
NAME
FUNCTION
RESET IN2
V_CC
CSRT
GND
RESET2
R2
RESET1
R1
MR
Input Voltage for RESET2 Monitor. High-impedance input for internal reset
comparator. Connect this pin to an external resistive-divider network to set the reset
threshold voltage.
Supply Voltage and Input Voltage for Primary Supply Monitor
RESET2 Delay Set Capacitor. Connect to V_CC for a fixed 140ms (min) timeout period
or to an external capacitor for a user-adjustable timeout period after V_CC exceeds its
minimum threshold.
Ground
Secondary Reset Output, Open-Drain, Active-Low. RESET2 changes from high to low
when either V_CC or RESET IN2 drop below their thresholds. RESET2 remains low for a
user-adjustable timeout period (see CSRT) or a fixed 140ms (min) after V_CC and
RESET IN2 meet their minimum thresholds.
47kΩ Internal Pullup Resistor for RESET2. Connect to external voltage for RESET2
high pullup.
Primary Reset Output, Open-Drain (MAX6391) or Push-Pull (MAX6392), Active-Low.
RESET1 changes from HIGH to LOW when the V_CC input drops below the selected
reset threshold. RESET1 remains LOW for the reset timeout period after V_CC exceeds
the minimum threshold.
47kΩ Internal Pullup Resistor for RESET1. Connect to external voltage for RESET1
high pullup.
Manual Reset, Active-Low, Internal 47kΩ Pullup to V_CC. Pull LOW to force a reset.
RESET1 and RESET2 remain asserted as long as MR is LOW and for the RESET1 and
RESET2 timeout periods after MR goes HIGH. Leave unconnected or connect to V_CC
if unused.
Detailed Description
Each device includes a pair of voltage monitors with
sequenced reset outputs. The first block monitors V_CC
only (RESET1 output is independent of the RESET IN2
monitor). It asserts a reset signal (LOW) whenever V_CC
is below the preset voltage threshold. RESET1 remains
asserted for at least 140ms after V_CC rises above the
reset threshold. RESET1 timing is internally set in each
device. V_CC voltage thresholds are available from
1.57V to 4.63V. In all cases V_CC acts as the master
supply (all resets are asserted when V_CC goes below
its selected threshold). The V_CC input also acts as the
device power supply.
The second block monitors both RESET IN2 and V_CC. It
asserts a reset signal (LOW) whenever RESET IN2 is
below the 625mV threshold or V_CC is below its reset
threshold. RESET2 remains asserted for a fixed 140ms
(min) or a user-adjustable time period after RESET IN2
rises above the 625mV reset threshold and RESET1 is
deasserted. Resets are guaranteed valid for V_CC down
to 1V.
The timing diagram in Figure 2 shows the reset timing
characteristics of the MAX6391/MAX6392. As shown in
Figure 2, RESET1 deasserts 140ms (min) (t_RP1) after
V_CC exceeds the reset threshold. RESET2 deasserts
t_RP2 (140ms minimum or a user-adjustable timeout peri-
od) after RESET IN2 exceeds 625mV and RESET1 is
deasserted. When RESET IN2 drops below 625mV
while V_CC is above the reset threshold, RESET2 asserts
within 10µs typ. RESET1 is unaffected when this hap-
pens. When V_CC falls below V_TH1, RESET2 always
asserts before RESET1 (t_RD2 < t_RD1).
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