MAX3866 Datasheet, PDF (5/12 Pages) Maxim Integrated Products – 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier

2.5Gbps, +3.3V Combined
Transimpedance/Limiting Amplifier
Typical Operating Circuits
3.3V
C_HF
100nF
CHF-
VCCS
FIL
IN+
IN-
GND
CHF+
VCCD
LOP
MAX3866
OUT+
OUT-
PDC INV CPD- CPD+
R_PD*
510Ω
10nF
100nF
OUT+
OUT-
100nF
5.0V
C_HF
100nF
CHF-
VCCS
FIL
IN+
IN-
GND
CHF+
VCCD
LOP
MAX3866
OUT+
OUT-
PDC INV CPD- CPD+
R_PD*
510Ω
100nF
OUT+
OUT-
100nF
3.3V OPERATION
* NOTE: IF LOP OPERATION IS NOT DESIRED, R_PD = 0Ω
5.0V OPERATION
Circuit Description
Data Path
The combined preamplifier and limiting postamplifier
(Figure 1) accepts an input current from a photodiode
attached to the input pad IN+. The transimpedance
input amplifier stage converts the input current to an
output voltage with a typical transimpedance of 1.4kΩ.
The second stage of the data path is an active high-
pass filter. This filter converts the single-ended input
signal to a differential signal, eliminating the DC com-
ponent and adding approximately 16dB of gain. The
output of the highpass filter drives the power detector
and limiting amplifier circuitry.
The limiting amplifier circuit is the third stage of the
data signal path. It amplifies and limits the differential
input signal. The output stage is a differential pair with
internal 50Ω load resistors. The limited output voltage is
typically 145mVp-p.
Power Detector
The power detect circuit consists of an adjustable-gain
amplifier and combined rectifier with a lowpass filter.
The adjustable-gain amplifier is controlled by an op amp.
The gain is adjusted by means of an external resistor
connected between the PDC and INV pins.
The output voltage of the adjustable gain amplifier
drives the combined rectifier and lowpass filter circuit-
ry. The resulting DC voltage is fed to a Schmitt trigger,
which generates a high-level output signal if the DC
input signal is below the LOP assert level, thus causing
an LOP condition on the LOP output.
Design Procedure
Power Supply
The complete amplifier is supplied by a single supply
voltage, V_CCD. For operation at 3.3V, the supply volt-
age is applied at both the VCCD and VCCS pins (see
Typical Operating Circuit). For operation at 5.0V, the
voltage is only applied at VCCD. In this case, VCCS is
on-chip controlled to approximately 3.2V. In the 5.0V
configuration, an external 10nF grounded capacitor is
required at the VCCS pin.
External Filter Capacitor C_HF
The value of C_HF affects the maximum speed at which
the compensation loop adjusts the input offset current.
C_HF should be chosen between 10nF and 100nF. The
loop should be as slow as possible to reduce pattern-
dependent jitter. Maxim recommends a value of C_HF =
100nF.
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