MAX16826_11 Datasheet, PDF (5/26 Pages) Maxim Integrated Products – Programmable, Four-String HB LED Driver with Output-Voltage Optimization and Fault Detection

Programmable, Four-String HB LED Driver with
Output-Voltage Optimization and Fault Detection
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 12V, R19 = 2kΩ, C33 = 2200pF, R17 = 1.27kΩ, C_{DL_} = 0.01μF, T_J = -40°C to +125°C, unless otherwise noted. Typical values
are at T_A = +25°C.) (Note 1)
PARAMETER
ADC (DR1–DR4, OVP)
Maximum Error
ADC Single Bit Acquisition
Latency
SYMBOL
CONDITIONS
E_MAX
(Note 4)
MIN TYP MAX UNITS
±50
mV
2
μs
DR Channel Sample Time
t_DR,SMPL
OVP Channel Sample Time
t_OVP,SMPL
Full-Scale Input Voltage
V_FS
Least Significant Bit
V_LSB
DR Input Bias Current
I_DR
0V < V_{DR_} < 5.5V
DRAIN FAULT COMPARATORS (DR1–DR4) (Shorted LED String Comparator)
190
ms
20
μs
1.215 1.24 1.2550
V
9.76
mV
-100
0
+100
nA
Drain Fault Comparator
Threshold
V_DFTH
Voltage to drive DL1–DL4 low
1.4 1.52 1.63
V
Drain Fault Comparator Delay
t_DFD
LINEAR REGULATORS (DL1–DL4, CS1–CS4)
Transconductance
Gm
Maximum Output Current
I_DL
CS1–CS4 Input Bias Current
I_CS
CS1–CS4 Regulation Voltage
Maximum
V_CS,MAX
10mV overdrive
ΔI = -500μA
Sourcing or sinking
0V < V_CS < 5.5V
CS_ = DL_, FB DAC full scale;
MAX16826 only
CS_ = DL_, FB DAC full scale;
MAX16826B only
1
μs
75
mS
15
mA
-100
0
+100
nA
306 316 324
mV
308 318 328
CS1–CS4 Regulation Voltage
Minimum
V_CS,MIN
CS_ = DL_, FB DAC minus full scale;
MAX16826 only
CS_ = DL_, FB DAC minus full scale;
MAX16826B only
90
97
105
mV
90
99
109
CS1–CS4 Regulation Voltage LSB
V_CS,LSB
CS_ = DL_, FB DAC 1-bit transition
1.72
mV
Note 1: All devices are 100% production tested at T_J = +25°C and T_J = +125°C. Limits to -40°C are guaranteed by design.
Note 2: I_CC includes the internal bias currents and the current used by the gate drivers to drive DL, DL1, DL2, DL3, and DL4.
Note 3: Minimum frequency to allow the internal ADC to complete at least one measurement. t_ON is the on-time with the LED current
in regulation.
Note 4: Minimum LED current pulse duration, which is required to correctly acquire 1 bit.
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