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MAX1361_06 Datasheet, PDF (5/24 Pages) Maxim Integrated Products – 4-Channel, 10-Bit, System Monitors with Programmable Trip Window and SMBus Alert Response
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1361), VDD = 4.5V to 5.5V (MAX1362), VREF = 2.048V (MAX1361), VREF = 4.096V (MAX1362), CREF =
0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Hold Time for START (S)
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition (Sr)
SYMBOL
tHD, STA
tLOW
tHIGH
tSU, STA
CONDITIONS
MIN TYP MAX UNITS
0.6
µs
1.3
µs
0.6
µs
0.6
µs
Data Hold Time
tHD, DAT
0
Data Setup Time
tSU, DAT
100
Rise Time of Both SDA and SCL
Signals, Receiving
tR
Measured from 0.3VDD to 0.7VDD
0
900
ns
ns
300
ns
Fall Time of SDA Transmitting
tF
Measured from 0.3VDD to 0.7VDD
0
Setup Time for STOP (P)
Condition
tSU, STO
0.6
300
ns
µs
Capacitive Load for Each Bus
Line
CB
400
pF
Pulse Width of Spike Suppressed
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Figures 1a, 2) (Note 12)
Serial Clock Frequency
fSCLH (Note 13)
Hold Time, Repeated START
Condition (Sr)
tHD, STA
160
50
ns
1.7
MHz
ns
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition (Sr)
tLOW
tHIGH
tSU, STA
(Note 13)
320
ns
120
ns
160
ns
Data Hold Time
tHD, DAT (Note 14)
0
Data Setup Time
tSU, DAT
10
Rise Time of SCL Signal
tRCL
Measured from 0.3VDD to 0.7VDD
20
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1 Measured from 0.3VDD to 0.7VDD
20
150
ns
ns
80
ns
160
ns
Fall Time of SCL Signal
tFCL
Measured from 0.3VDD to 0.7VDD
20
Rise Time of SDA Signal
tRDA Measured from 0.3VDD to 0.7VDD
20
Fall Time of SDA Signal
tFDA
Measured from 0.3VDD to 0.7VDD
20
Setup Time for STOP (P)
Condition
tSU, STO
160
Capacitive Load for Each Bus
CB
Pulse Width of Spike Suppressed
0
80
ns
160
ns
160
ns
ns
400
pF
10
ns
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